# US 9,520,160 B2 · Printed circuit board and memory module including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,160 B2 - Document ID: US9520160B2 - Status: Granted - Kind: B2 - Application number: 14/229,483 - Filed: 2014-03-28 - Published: 2014-10-09 - Granted: 2016-12-13 - Earliest claimed: 2013-04-05 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Chil-Nam Yoon; Seon-Ryeong Kang; Hui-Chong Shin - Web page: https://patentgrep.com/patent/US9520160B2 ## CPC - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 7/109: {Control signal input circuits} - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - H05K 1/0253: {Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings (H05K1/0251 takes precedence)} - G11C 2207/105: Aspects related to pads, pins or terminals - H05K 1/0225: {Single or multiple openings in a shielding, ground or power plane (H05K1/0227 takes precedence)} - H05K 2201/09327: Special sequence of power, ground and signal layers in multilayer PCB - H05K 2201/10159: Memory - G11C: STATIC STORES (semiconductor memory devices H10B) - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A memory module includes a plurality of semiconductor memory devices and a circuit board. The circuit board is electrically connected to the plurality of semiconductor memory devices, and a signal line is disposed in the outermost layer of the circuit board. An electrical reference for the signal line is provided in a layer of the circuit board that is not adjacent to the outermost layer. Accordingly, an impedance of the signal line may be increased, and signal integrity of a signal transmitted through the signal line may be improved. ## Claims ### Claim 1 A memory module, comprising: a semiconductor memory device; and a circuit board coupled to the semiconductor memory device, the circuit board including an outer layer disposed below the semiconductor memory device, an inner layer disposed below the outer layer, and an intermediate layer disposed between the inner and outer layers, wherein the outer layer includes a first signal line electrically connected to the semiconductor memory device, the inner layer includes a reference conductive region configured to provide an electrical reference for the first signal line, and the intermediate layer includes intermediate conductive regions. ### Claim 2 (depends on 1) The memory module of claim 1, wherein the circuit board comprises a command/address signal area that includes the first signal line, the reference conductive region, the intermediate conductive regions, and a signal layer disposed below the inner layer, wherein the intermediate conductive regions comprise a power/ground plane, the signal layer includes a second signal line electrically connected to the outer layer through a via connecting the outer layer to the signal layer, and the inner layer includes a third signal line, wherein the reference conductive region disposed in the inner layer comprises a conductive plane configured to provide the electrical reference for the first signal line disposed in the outer layer. ### Claim 3 (depends on 2) The memory module of claim 2, wherein there are no conductive regions disposed in the intermediate layer directly below the first signal line disposed in the outer layer. ### Claim 4 (depends on 2) The memory module of claim 2, wherein the second signal line disposed in the signal layer is a command/address signal line electrically connected to the semiconductor memory device. ### Claim 5 (depends on 1) The memory module of claim 1, wherein the intermediate layer comprises a slit disposed directly below the first signal line disposed in the outer layer. ### Claim 6 (depends on 1) The memory module according to claim 1, wherein the circuit board comprises a data area that includes: a signal layer disposed below the inner layer, the signal layer having a second signal line, a power/ground layer disposed below the signal layer, the power/ground layer having a power/ground reference plane configured to provide an electrical reference for the second signal line, a third signal line disposed in the inner layer, and a via connecting the third signal line to the semiconductor memory device. ### Claim 7 (depends on 6) The memory module according to claim 6, wherein the power/ground reference plane comprises at least one of a power plane and a ground plane. ### Claim 8 (depends on 1) The memory module according to claim 1, wherein the circuit board comprises a data area that includes: a power/ground plane disposed in the intermediate layer, a second signal line disposed in the inner layer, a via connecting the outer layer to the inner layer, and a signal layer disposed below the inner layer, the signal layer including a third signal line. ### Claim 9 (depends on 8) The memory module according to claim 8, wherein the via connecting the outer layer to the inner layer connects the second signal line disposed in the inner layer to the semiconductor memory device. ### Claim 10 (depends on 8) The memory module according to claim 8, wherein the power/ground plane disposed in the intermediate layer is configured to provide an electrical reference for the second signal line disposed in the lower inner layer. ### Claim 11 (depends on 8) The memory module according to claim 8, further comprising a power/ground layer disposed below the signal layer, the power/ground layer including a power plane or a ground plane, and the power or ground plane is configured to provide an electrical reference for the third signal line disposed in the signal layer. ### Claim 12 (depends on 1) The memory module according to claim 1, wherein the circuit board further comprises: a signal layer disposed below the inner layer, a second inner layer disposed below the signal layer, a second intermediate layer disposed below the second inner layer, a second outer layer disposed below the second intermediate layer, wherein a second semiconductor memory device coupled to the circuit board below the second outer layer, wherein the second outer layer includes a second signal line electrically connected to the second semiconductor memory device, the second inner layer includes a second reference conductive region configured to provide an electrical reference for the second signal line, and the second intermediate layer includes second intermediate conductive regions. ### Claim 13 (depends on 12) The memory module according to claim 12, further comprising a signal layer disposed between the inner layer and the second inner layer, the signal layer including a third signal line, a via connecting the first signal line to the third signal line, and a second via connecting the second signal line to the first signal line. ### Claim 14 (depends on 1) The memory module of claim 1, further comprising a dielectric material disposed between the outer layer and the intermediate layer, and a dielectric material disposed between the intermediate layer and the inner layer. ### Claim 15 A printed circuit board, comprising: a first layer including a first signal line; a second layer disposed below the first layer, the second layer including a power or ground plane; a third layer disposed below the second layer, the third layer including a second signal line and a partial plane; a fourth layer disposed below the third layer, the fourth layer including a third signal line; and a via connecting the first layer to the third signal line disposed in the fourth layer, wherein the partial plane disposed in the third layer is configured to provide an electrical reference for the first signal line disposed in the first layer. ### Claim 16 (depends on 15) The printed circuit board according to claim 15, wherein the second layer does not include any conductive regions directly below the first signal line. ### Claim 17 (depends on 15) The printed circuit board according to claim 15, wherein the second layer comprises a slit disposed directly below the first signal line. ### Claim 18 (depends on 15) The printed circuit board according to claim 15, further comprising a third signal line disposed in the first layer, and an insulator placed between the first layer and the second layer, wherein a portion of the power or ground plane is disposed directly below the third signal line and the third signal line and the power or ground plane are electrically separated by the insulator. ### Claim 19 A method of providing a memory module, comprising: providing a semiconductor memory device; and providing a circuit board including an outer layer having a first signal line electrically connected to the semiconductor memory device, an inner layer having a reference conductive region configured to provide an electrical reference for the first signal line disposed below the outer layer, and an intermediate layer having conductive regions disposed between the inner and outer layers. ### Claim 20 (depends on 19) The method of claim 19, wherein the step of providing a circuit board further comprises providing a circuit board including a signal layer having a second signal line disposed below the inner layer, and a via connecting the first and second signal lines.