# US 9,519,943 B2 · Priority-based command execution

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- Number: US 9,519,943 B2
- Document ID: US9519943B2
- Status: Granted
- Kind: B2
- Application number: 13/171,979
- Filed: 2011-06-29
- Published: 2012-06-07
- Granted: 2016-12-13
- Earliest claimed: 2010-12-07
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Philip J. Rogers; David Gotwalt; Tom Frisinger; Rex McCrary
- Inventors: Philip J. Rogers; David Gotwalt; Tom Frisinger; Rex McCrary
- Web page: https://patentgrep.com/patent/US9519943B2

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 9/4818: {Priority circuits therefor}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/5044: {considering hardware capabilities}
- G06F 2209/5021: Priority
- G06F 2209/509: Offload
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of processing commands is provided. The method includes holding commands in queues and executing the commands in an order based on their respective priority. Commands having the same priority are held in the same queue.

## Claims

### Claim 1

A method comprising:
creating, at a central processing unit (CPU), a plurality of virtual devices, each of the virtual devices abstracting a graphics processing unit (GPU) to create a virtual GPU within the CPU, wherein each of the plurality of virtual devices is associated with a respective priority;
receiving a first command in a queue of a first virtual device of the plurality of virtual devices, wherein a priority associated with the first command matches a priority associated with the first virtual device; and
sending the first command from the first virtual device in the CPU to a GPU; and
executing, at the GPU, the first command.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
sending a second command from a queue of a second virtual device of the plurality of virtual devices in the CPU to the GPU before the first command is sent, wherein a priority associated with the second command is higher than the priority associated with the first command.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
sending commands from queues of the plurality of virtual devices in the CPU to the GPU in a round-robin manner.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
receiving the first command in a queue in the GPU.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
sending a result of the first command from the GPU to the CPU.

### Claim 6 (depends on 4)

The method of claim 4, further comprising:
retrieving, at the GPU, the first command from the queue of the GPU; and
updating, at the GPU, a head pointer and a tail pointer associated with the queue based on the retrieving.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
determining, at the GPU, that processing resources sufficient to begin execution of the first command are available; and
executing, at the GPU, the first command using the processing resources.

### Claim 8 (depends on 1)

The method of claim 1, wherein the plurality of virtual devices comprises a high priority virtual device and a low priority virtual device.

### Claim 9 (depends on 8)

The method of claim 8, wherein the plurality of virtual devices further comprises a mid-priority virtual device.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
interrupting the first command currently executing on the GPU; and
executing a first command.

### Claim 11

A processing device, comprising:
a set of queues, each queue of the set of queues being configured to hold commands received from a central processing unit (CPU), wherein each command is sent from a virtual device in the CPU;
a command processor configures to retrieve the received commands from the set of queues, wherein the set of queues includes a high priority queue that holds high priority commands, wherein the command processor is configured to retrieve a high priority command held in the high priority queue before retrieving commands held in other queues of the set of queues, and wherein the processing device is configured to executed the received commands; and
a processing core configured to execute the received command, wherein the command processor is configured to retrieve commands from the set of queues and send the retrieved commands to the processing core for execution.

### Claim 12 (depends on 11)

The processing device of claim 11, wherein each of the queues comprises a ring buffer.

### Claim 13 (depends on 12)

The processing device of claim 12, wherein the command processor comprises first and second registers for each queue of the set of queues, wherein the first and second registers are configured to store a head pointer and tail pointer, respective queue of the set of queues.

### Claim 14 (depends on 11)

The processing device of claim 11, wherein the processing core comprises processing resources, wherein the command processor is configured to send the high priority command to the processing core if processing resources sufficient to execute the high priority command are available in the processing device.

### Claim 15 (depends on 11)

The processing device of claim 11, wherein the processing core comprises processing resources, wherein the command processor is configured to determine when processing resources sufficient to execute the high priority command are available.

### Claim 16 (depends on 11)

The processing device of claim 11, wherein the command processor is configured to preempt execution of the processing device to execute the high priority command.

### Claim 17 (depends on 11)

The processing device of claim 11, further comprising a run list controller configured to control the command processor.

### Claim 18 (depends on 11)

The processing device of claim 11, wherein the processing device is configured to store a head pointer and a tail pointer respective to each queue of the set of queues in a memory.

### Claim 19

A system for processing commands, comprising:
a central processing unit (CPU) configured to generate commands, wherein each command is sent from a virtual device in the CPU; and
a graphics processing unit (GPU) coupled to the CPU and configured to receive the commands from a set of queues, each queue of the set of queues being configured to hold the received commands; and
a command processor configured to retrieve the received commands from the set of queues, wherein the set of queues include a high priority queue that holds high priority commands, wherein the command processor is configured to retrieve a high priority command held in the high priority queue before retrieving commands held in other queues of the set of queues, and wherein the GPU is configured to executed the received commands.

### Claim 20 (depends on 19)

The system of claim 19, wherein each of the queues comprises a ring buffer.

### Claim 21 (depends on 20)

The system of claim 20, wherein the command processor comprises first and second registers for each queue of the set of queues, wherein the first and second registers store a head pointer and tail pointer, respectively, for a respective queue of the set of queues.

### Claim 22 (depends on 19)

The system of claim 19, wherein the CPU executes an instance of a user mode driver for a process running on the CPU and wherein the user mode driver instance generates the commands.

### Claim 23 (depends on 22)

The system of claim 22, wherein the CPU is configured to create virtual devices for the user mode driver instance, wherein each of the virtual devices includes a queue configured to hold commands.

### Claim 24 (depends on 22)

The system of claim 22, wherein the CPU executes a kernel mode driver configured to fetch commands from each of the queues of the virtual devices and to send commands to the GPU.