# US 9,519,806 B2 · Domain-specific hardwired web server machine

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- Number: US 9,519,806 B2
- Document ID: US9519806B2
- Status: Granted
- Kind: B2
- Application number: 14/321,097
- Filed: 2014-07-01
- Published: 2016-01-07
- Granted: 2016-12-13
- Earliest claimed: 2014-07-01
- Assignees: Hackproof Technologies Inc.
- Applicants: Hackproof Technologies, Inc.
- Inventors: Joseph Mitola, III
- Web page: https://patentgrep.com/patent/US9519806B2

## CPC

- G06N 20/00: Machine learning
- G06F 9/524: {Deadlock detection or avoidance}
- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G06F 11/0721: {within a central processing unit [CPU]}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F 21/56: Computer malware detection or handling, e.g. anti-virus arrangements
- G06F 21/57: Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F 21/71: to assure secure computing or processing of information
- G06F 21/76: in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06Q 20/405: {Establishing or using transaction specific rules}
- H04L 47/70: Admission control; Resource allocation
- H04L 63/123: {received data contents, e.g. message integrity}
- H04L 67/02: based on web technology, e.g. hypertext transfer protocol [HTTP]
- Y02D 30/00: Reducing energy consumption in communication networks
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06Q: INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A domain-specific hardwired symbolic web server machine is described that processes information via the hardwired mapping of symbols from one or more domains onto other such domains, computing and communicating with improved security and reduced power consumption because it has no CPU, no Random Access Memory (RAM), no instruction registers, no Instruction Set Architecture (ISA), no operating system (OS) and no applications programming. The machine provides web services by recognizing legal requests such as HTTP GET request and responding with an HTML web page. In some embodiments, the machine has no unconstrained RAM into which malware may insert itself and needs no anti-virus software.

## Claims

### Claim 1

A domain-specific web server apparatus comprising:
first circuitry configured to receive a hypertext transfer protocol (HTTP) request;
second circuitry configured to generate an input symbol based on the HTTP request;
third circuitry configured to validate that a value of the input symbol is valid according to a first domain, wherein the first domain is one of a plurality of domains embedded into hardware of the domain-specific web server apparatus, wherein the first domain includes, via a hardwired symbolic notation, values that the HTTP request is allowed to have;
fourth circuitry configured to generate an output symbol by mapping the input symbol from the first domain to a second domain of the plurality of domains;
fifth circuitry configured to determine output data based on the output symbol; and
sixth circuitry configured to transmit the output data as a response to the HTTP request.

### Claim 2 (depends on 1)

The domain-specific web server apparatus of claim 1, wherein the domain-specific web server apparatus has no registers; no central processing unit (CPU); no Random Access Memory (RAM); no instruction registers; no Instruction Set Architecture (ISA); has no operating system (OS); and has no applications programming.

### Claim 3 (depends on 1)

The domain-specific web server apparatus of claim 1, wherein the output data includes a web page.

### Claim 4 (depends on 1)

The domain-specific web server apparatus of claim 1, wherein the values of the first domain include a first value for a ‘SYN’ object and a second value for a ‘GET’ object.

### Claim 5 (depends on 1)

The domain-specific web server apparatus of claim 1, wherein the HTTP request includes an HTTP SYN request or an HTTP GET request.

### Claim 6 (depends on 1)

The domain-specific web server apparatus of claim 1 further comprising:
seventh circuitry configured to store a computational self-description of the domain-specific web server apparatus, wherein the computational self-description provides a description of what the domain-specific web server apparatus is configured to perform.

### Claim 7 (depends on 1)

The domain-specific web server apparatus of claim 1 further comprising:
seventh circuitry configured to cause the domain specific web server apparatus to ignore the HTTP request if the value of the input symbol is invalid.

### Claim 8 (depends on 1)

The domain-specific web server apparatus of claim 1, embodied in one or more field-programmable gate arrays (FPGA) or one or more application-specific integrated circuits (ASIC).

### Claim 9

An apparatus comprising:
one or more field programmable gate arrays programmed, via one or more field programmable gate array (FPGA) images, to cause the apparatus to:
receive a hypertext transfer protocol (HTTP) request;
generate an input symbol based on the HTTP request;
validate that a value of the input symbol is valid according to a first domain, wherein the first domain is one of a plurality of domains embedded into hardware of the one or more field programmable gate arrays, wherein the first domain includes, via a hardwired symbolic notation, values that the HTTP request is allowed to have;
generate an output symbol by mapping the input symbol from the first domain to a second domain of the plurality of domains;
determine output data based on the output symbol; and
transmit the output data as a response to the HTTP request.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the apparatus has no registers; no central processing unit (CPU); no Random Access Memory (RAM); no instruction registers; no Instruction Set Architecture (ISA); has no operating system (OS); and has no applications programming.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein the output data includes a web page.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein the values of the first domain include a first value for a ‘SYN’ object and a second value for a ‘GET’ object.

### Claim 13 (depends on 9)

The apparatus of claim 9, wherein the HTTP request includes an HTTP SYN request or an HTTP GET request.

### Claim 14 (depends on 9)

The apparatus of claim 9, wherein the one or more field programmable gate arrays are programmed, via the one or more FPGA images, to cause the apparatus to:
store a computational self-description of the apparatus, wherein the computational self-description provides a description of what the apparatus is configured to perform.

### Claim 15 (depends on 9)

The apparatus of claim 9, wherein the one or more field programmable gate arrays are programmed, via the one or more FPGA images, to cause the apparatus to:
ignore the HTTP request if the value of the input symbol is invalid.

### Claim 16

A method comprising:
receiving a definition of one or more functions for a hypertext transfer protocol (HTTP) web server to be implemented in an apparatus, wherein the one or more functions include transmitting a response to a received HTTP request;
determining a list of domains, a list of variable objects and a list of maps based on the definition;
determining, based on the list of domains, domain validation pipe circuitry to produce a plurality of domain validation pipe circuits that are each configured to validate input as having a valid value according to at least one domain in the list of domains;
determining, based on the list of maps, domain mapping pipe circuitry to produce a plurality of domain mapping pipe circuits that are each configured to map input between a first domain in the list of domains to a second domain in the list of domains;
determining, based on the list of variable objects, memory block circuitry to produce a plurality of memory block circuits, the plurality of memory block circuits being configured to (a) provide input to and receive output from the plurality of domain validation pipe circuits and (b) provide input to and receive output from the plurality of domain mapping pipe circuits; and
implementing the plurality of domain validation pipe circuits, the plurality of domain mapping pipe circuits and the plurality of memory block circuits into the apparatus such that the apparatus is configured to perform the one or more functions for the HTTP web server.

### Claim 17 (depends on 16)

The method of claim 16, wherein the apparatus comprises a field programmable gate array (FPGA), and wherein the implementing the plurality of domain validation pipe circuits, the plurality of domain mapping pipe circuits and the plurality of memory block circuits into the apparatus includes:
converting the plurality of domain validation pipe circuits, the plurality of domain mapping pipe circuits and the plurality of memory block circuits into an FPGA image, and
compiling the FPGA image into the FPGA such that the FPGA is configured to perform the one or more functions for the HTTP web server.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
determining a list of constraints based on the definition; and
determining self-description circuitry based on the list of constraints, wherein the self-description defines what the apparatus is configured to perform;
wherein the implementing the plurality of domain validation pipe circuits, the plurality of domain mapping pipe circuits and the plurality of memory block circuits into the apparatus includes implementing the self-description circuitry into the apparatus.

### Claim 19 (depends on 16)

The method of claim 16, wherein the plurality of domain validation pipe circuits includes a first pipe circuit that determines whether a textual symbol has a valid value according to a first domain from the list of domains; and
wherein the plurality of domain mapping pipe circuits includes a second pipe circuit that maps the textual symbol from the first domain to a second domain from the list of domains.

### Claim 20 (depends on 16)

The method of claim 16, wherein after implementing the plurality of domain validation pipe circuits, the plurality of domain mapping pipe circuits and the plurality of memory block circuits into the apparatus, the apparatus is configured to perform the one or more functions for the HTTP web server without using an Instruction Set Architecture (ISA).