# US 9,519,773 B2 · Returning to a control transfer instruction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,519,773 B2 - Document ID: US9519773B2 - Status: Granted - Kind: B2 - Application number: 14/484,751 - Filed: 2014-09-12 - Published: 2016-03-17 - Granted: 2016-12-13 - Earliest claimed: 2014-09-12 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Baiju Patel; Vedvyas Shanbhogue; Ravi Sahita - Web page: https://patentgrep.com/patent/US9519773B2 ## CPC - G06F 21/52: during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} - G06F 9/30003: {Arrangements for executing specific machine instructions} - G06F 9/30054: {Unconditional branch instructions} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 21/74: operating in dual or compartmented mode, i.e. at least one secure mode - G06F 2221/033: Test or assess software - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In an embodiment, the present invention includes a processor having a decode unit and an execution unit. The decode unit is to decode control transfer instructions and the execution unit is to execute control transfer instructions, the control transfer instructions including a call instruction and a return instruction. The processor is to operate in a first mode in which the processor is to raise a fault if a next instruction to be executed immediately after the return instruction is not the call instruction. ## Claims ### Claim 1 A processor to operate in a first mode and a second mode, comprising: front-end hardware including: a decoder to decode a plurality of control transfer instructions, the plurality of control transfer instructions including a call instruction and a return instruction; and a state machine to raise a fault in the first mode if a next instruction to be executed immediately after the return instruction is not the call instruction; wherein, in the first mode, execution of the call instruction is to include pushing on a stack an address of the call instruction, and wherein, in the second mode, execution of the call instruction is to include pushing on the stack an address of an instruction immediately following the call instruction. ### Claim 2 (depends on 1) The processor of claim 1, wherein, in the first mode, execution of the return instruction includes arming a state of the state machine to cause a next instruction to be executed immediately after the return instruction to be executed as a no-operation instruction if it is the call instruction. ### Claim 3 (depends on 2) The processor of claim 2, wherein, in the first mode, the state is disarmed in response to popping the call instruction from the stack by execution of the return instruction when the state is armed. ### Claim 4 (depends on 2) The processor of claim 2, wherein the state is saved in connection with a context switch. ### Claim 5 (depends on 2) The processor of claim 2, wherein the state is saved in connection with a change to a processor privilege level. ### Claim 6 A method comprising: decoding, by a processor, a call instruction; executing, if the processor is in a first mode, the call instruction, including pushing on a stack an address of the call instruction; executing, if the processor is in a second mode, the call instruction, including pushing on the stack an address of an instruction immediately following the call instruction; decoding, by the processor, a return instruction; determining, by the processor in the first mode, whether a next instruction immediately after the return instruction is not a call instruction; and raising a fault in response to determining, in the first mode, that the next instruction is not a call instruction. ### Claim 7 (depends on 6) The method of claim 6, further comprising executing, in the first mode, the return instruction, including arming a state to cause a next instruction to be executed immediately after the return instruction to be executed as a no-operation instruction if it is the call instruction. ### Claim 8 (depends on 7) The method of claim 7, further comprising, in the first mode, disarming the state in response to popping the call instruction from the stack by execution of the return instruction when the state is armed. ### Claim 9 (depends on 7) The method of claim 7, further comprising saving the state in connection with a context switch. ### Claim 10 (depends on 7) The method of claim 7, further comprising saving the state in connection with a change to a processor privilege level. ### Claim 11 (depends on 7) The method of claim 7, further comprising matching, by software running on the processor, the return instruction to the call instruction. ### Claim 12 A system comprising: a memory including a sequence of instructions to be executed by a processor, the sequence of instructions including a call instruction and a return instruction; and the processor, including a decode unit to decode the sequence of instructions, and an execution unit to execute the sequence of instructions; wherein the processor is to operate in a first mode in which execution of the call instruction is to include pushing on a stack a memory address of the call instruction and in which the processor is to raise a fault if a next instruction to be executed immediately after the return instruction is not the call instruction; and wherein the processor is also to operate in a second mode in which execution of the call instruction is to include pushing on the stack a memory address of an instruction immediately following the call instruction. ### Claim 13 (depends on 12) The system of claim 12, wherein, in the first mode, execution of the return instruction includes arming a state to cause a next instruction to be executed immediately after the return instruction to be executed as a no-operation instruction if it is the call instruction. ### Claim 14 (depends on 13) The system of claim 13, wherein, in the first mode, the state is disarmed in response to popping the call instruction from the stack by execution of the return instruction when the state is armed.