# US 9,519,745 B2 · Method and apparatus for assisted metal routing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,519,745 B2 - Document ID: US9519745B2 - Status: Granted - Kind: B2 - Application number: 14/523,558 - Filed: 2014-10-24 - Published: 2016-04-28 - Granted: 2016-12-13 - Earliest claimed: 2014-10-24 - Assignees: Globalfoundries Inc. - Applicants: GLOBALFOUNDRIES Inc. - Inventors: Lei Yuan; Irene Lin; Jongwook Kye; Mahbub Rashed - Web page: https://patentgrep.com/patent/US9519745B2 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method and apparatus for an assisted metal routing is disclosed. Embodiments may include: determining an initial block mask having a first inner vertex for forming a metal routing layer of an integrated circuit (IC); adding an assistant metal portion within the metal routing layer; and determining a modified block mask based on the assistant metal portion for forming the metal routing layer. ## Claims ### Claim 1 A method comprising: determining an initial block mask having a first inner vertex for forming a metal routing layer of an integrated circuit (IC); adding an assistant metal portion within the metal routing layer; determining a modified block mask based on the assistant metal portion for forming the metal routing layer; determining a first line end of the metal routing layer; determining a first VIA connection to the metal routing layer at the first line end determining a second line end of the metal routing layer within a same track as the first line end; determining a second VIA connection to the metal routing layer at the second line end; and modifying the metal routing layer to connect the assistant metal portion to routing lines of the metal routing layer, the assistant metal portion providing a routing resource for a third VIA connection, wherein the first inner vertex of the initial block mask corresponds to forming the first line end, wherein the modified block mask satisfies a routing violation of the metal routing layer with respect to the first VIA connection, and wherein the modified block mask satisfies a routing violation of the metal routing layer between the first VIA connection and the second VIA connection. ### Claim 2 (depends on 1) The method according to claim 1, further comprising: determining a routing violation associated with the first inner vertex of the initial block mask, wherein the adding of the assistant metal portion is based on the routing violation. ### Claim 3 (depends on 2) The method according to claim 2, wherein the routing violation is based on one or more of a keep out rule, a vertical interconnect access (VIA) enclosure rule, and a minimum feature size for block masking. ### Claim 4 (depends on 1) The method according to claim 1, wherein the assistant metal portion is added to a metal track adjacent to the first line end. ### Claim 5 An apparatus comprising: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to perform at least the following: determine an initial block mask having a first inner vertex to form a metal routing layer of an integrated circuit (IC); add an assistant metal portion within the metal routing layer; determine a modified block mask based on the assistant metal portion for forming the metal routing layer; determine a first line end of the metal routing layer; determine a first VIA connection to the metal routing layer at the first line end; determine a second line end of the metal routing layer within a same track as the first line end; determine a second VIA connection to the metal routing layer at the second line end; and modify the metal routing layer to connect the assistant metal portion to routing lines of the metal routing layer, the assistant metal portion providing a routing resource for a third VIA connection, wherein the first inner vertex of the initial block mask corresponds to forming the first line end, wherein the modified block mask satisfies a routing violation of the metal routing layer with respect to the first VIA connection, and wherein the modified block mask satisfies a routing violation of the metal routing layer between the first VIA connection and the second VIA connection. ### Claim 6 (depends on 5) The apparatus according to claim 5, wherein the apparatus is further caused to: determine a routing violation associated with the first inner vertex of the initial block mask, wherein the adding of the assistant metal portion is based on the routing violation. ### Claim 7 (depends on 6) The apparatus according to claim 6, wherein the routing violation is based on one or more of a keep out rule, a vertical interconnect access (VIA) enclosure rule, and a minimum feature size for block masking. ### Claim 8 (depends on 5) The apparatus according to claim 5, wherein the assistant metal portion is added to a metal track adjacent to the first line end. ### Claim 9 A method comprising: determining a configuration of a metal routing layer of an integrated circuit (IC) that would cause a routing violation; adding an assistant metal portion to the metal routing layer; determining a block mask based on the assistant metal portion for forming the metal routing layer that satisfies the routing violation; and modifying the metal routing layer to connect the assistant metal portion to routing lines of the metal routing layer, wherein the routing violation is associated with a block mask inner vertex at an line end of the metal routing layer including a vertical interconnect access (VIA) connection, wherein the assistant metal portion provide a routing resource for the VIA connection. ### Claim 10 (depends on 9) The method according to claim 9, wherein the routing violation is based on one or more of a keep out rule, a VIA loop enclosure rule, and a minimum feature size for block masking.