# US 9,519,612 B2 · Serial bus buffer with noise reduction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,519,612 B2 - Document ID: US9519612B2 - Status: Granted - Kind: B2 - Application number: 14/160,900 - Filed: 2014-01-22 - Published: 2014-10-09 - Granted: 2016-12-13 - Earliest claimed: 2013-04-04 - Assignees: Qorvo US, Inc. - Applicants: RF Micro Devices, Inc. - Inventors: Alexander Wayne Hietala; Christopher Truong Ngo; Eric K. Bolton - Web page: https://patentgrep.com/patent/US9519612B2 ## CPC - G06F 13/4291: {using a clocked protocol} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface. ## Claims ### Claim 1 A serial bus buffer comprising: a primary interface coupled to a primary serial data line and a primary serial clock line of a primary bus, wherein the primary bus is coupled to a first device and at least one second device; a buffered interface coupled to a buffered serial data line and a buffered serial clock line of a buffered bus, wherein the buffered bus is coupled to at least one third device; and a controller coupled between the primary interface and the buffered interface and configured to: receive a first data signal and a clock signal at the primary interface; and replicate the first data signal and the clock signal at the buffered interface upon receiving a first command within the first data signal to execute a first mode that passes the first data signal and the clock signal from the primary interface to the buffered interface. ### Claim 2 (depends on 1) The serial bus buffer of claim 1 wherein the first device is a master device and the at least one third device is a sensitive slave device. ### Claim 3 (depends on 2) The serial bus buffer of claim 2 wherein the at least one second device is a non-sensitive slave device. ### Claim 4 (depends on 1) The serial bus buffer of claim 1 wherein the buffered bus comprises at least one filter and wherein the at least one filter reduces spurious signals coupled to the buffered bus. ### Claim 5 (depends on 4) The serial bus buffer of claim 4 wherein the at least one filter is a low corner frequency low pass filter. ### Claim 6 (depends on 1) The serial bus buffer of claim 1 wherein the controller is further configured to provide a high impedance output at the buffered interface such that the first data signal and the clock signal are not replicated at the buffered interface. ### Claim 7 A serial bus buffer comprising: a primary interface coupled to a primary serial data line and a primary serial clock line of a primary bus, wherein the primary bus is coupled to a first device and at least one second device; a buffered interface coupled to a buffered serial data line and a buffered serial clock line of a buffered bus, wherein the buffered bus is coupled to at least one third device; and a controller coupled between the primary interface and the buffered interface and configured to: receive a first data signal and a clock signal at the primary interface; select a first drive level from one of a first plurality of available drive levels; and replicate the first data signal and the clock signal at the first drive level at the buffered interface upon receiving a first command within the first data signal to execute a first mode that passes the first data signal and the clock signal from the primary interface to the buffered interface. ### Claim 8 (depends on 7) The serial bus buffer of claim 7 wherein the controller is further configured to: receive a second data signal at the buffered interface; and replicate the second data signal at the primary interface. ### Claim 9 (depends on 8) The serial bus buffer of claim 8 wherein the controller is further configured to: select a second drive level from a second plurality of available drive levels; and replicate the second data signal at the second drive level at the primary interface. ### Claim 10 (depends on 7) The serial bus buffer of claim 7 wherein the controller is further configured to: during a first mode, replicate the first data signal and the clock signal at the buffered interface; and during a second mode, the first data signal and the clock signal are not replicated at the buffered interface. ### Claim 11 (depends on 10) The serial bus buffer of claim 10 wherein during the second mode, the controller is further configured to provide a high impedance output at the buffered interface such that the first data signal and the clock signal are not replicated at the buffered interface. ### Claim 12 A serial bus buffer comprising: a primary interface coupled to a primary serial data line and a primary serial clock line of a primary bus, wherein the primary bus is coupled to a first device and at least one second device; a buffered interface coupled to a buffered serial data line and a buffered serial clock line of a buffered bus, wherein the buffered bus is coupled to at least one third device; and a controller coupled between the primary interface and the buffered interface and configured to: receive a first data signal and a clock signal at the primary interface; replicate the first data signal and the clock signal at the buffered interface upon receiving a first command within the first data signal to execute a first mode that passes the first data signal and the clock signal from the primary interface to the buffered interface; receive a second data signal at the buffered interface; and replicate the second data signal at the primary interface upon receiving a second command within the second data signal to execute a second mode that passes the second data signal and the clock signal from the buffer interface to the primary interface. ### Claim 13 (depends on 12) The serial bus buffer of claim 12 wherein the controller is further configured to: select a first drive level from a first plurality of available drive levels; and replicate the first data signal and the clock signal at the first drive level at the buffered interface. ### Claim 14 (depends on 13) The serial bus buffer of claim 13 wherein the controller is further configured to: select a second drive level from a second plurality of available drive levels; and replicate the second data signal at the second drive level at the primary interface. ### Claim 15 (depends on 12) The serial bus buffer of claim 12 wherein the controller is further configured to: during a first mode: replicate the first data signal and the clock signal at the buffered interface; receive the second data signal at the buffered interface; and replicate the second data signal at the primary interface; and during a second mode: the first data signal and the clock signal are not replicated at the buffered interface; the second data signal is not received at the buffered interface; and the second data signal is not replicated at the primary interface. ### Claim 16 (depends on 15) The serial bus buffer of claim 15 wherein during the second mode, the controller is further configured to provide a high impedance output at the buffered interface such that: the first data signal and the clock signal are not replicated at the buffered interface; the second data signal is not received at the buffered interface; and the second data signal is not replicated at the primary interface. ### Claim 17 A serial bus buffer comprising: a primary interface coupled to a primary serial data line and a primary serial clock line of a primary bus, wherein the primary bus is coupled to a first device and at least one second device; a buffered interface coupled to a buffered serial data line and a buffered serial clock line of a buffered bus, wherein the buffered bus is coupled to at least one third device; and a controller coupled between the primary interface and the buffered interface and to: receive a first data signal and a clock signal at the primary interface; during a first mode, replicate the first data signal and the clock signal at the buffered interface upon receiving a first command within the first data signal to execute the first mode that passes the first data signal and the clock signal from the primary interface to the buffered interface; and during a second mode, the first data signal and the clock signal are not replicated at the buffered interface upon receiving a second command within the first data signal to execute the second mode that blocks the passing of the first data signal and the clock signal from the primary interface to the buffered interface. ### Claim 18 (depends on 17) The serial bus buffer of claim 17 wherein the controller is further configured to operate in the second mode until receiving the first data signal. ### Claim 19 (depends on 17) The serial bus buffer of claim 17 wherein the controller is further configured to operate in the second mode until a predetermined condition. ### Claim 20 (depends on 17) The serial bus buffer of claim 17 wherein the controller is further configured to operate in the second mode for a duration of the predetermined condition. ### Claim 21 (depends on 17) The serial bus buffer of claim 17 wherein during the first mode, the controller is further configured to: receive a second data signal at the buffered interface; and replicate the second data signal at the primary interface. ### Claim 22 (depends on 17) The serial bus buffer of claim 17 wherein during the first mode, the controller is further configured to: select a first drive level from one of a first plurality of available drive levels; and replicate the first data signal and the clock signal at the first drive level at the buffered interface. ### Claim 23 (depends on 22) The serial bus buffer of claim 22 wherein during the first mode, the controller is further configured to: receive a second data signal at the buffered interface; select a second drive level from one of a second plurality of available drive levels; and replicate the second data signal at the second drive level at the primary interface.