# US 9,519,611 B2 · Hardware data structure for tracking ordered transactions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,519,611 B2 - Document ID: US9519611B2 - Status: Granted - Kind: B2 - Application number: 14/832,087 - Filed: 2015-08-21 - Published: 2016-03-03 - Granted: 2016-12-13 - Earliest claimed: 2014-09-02 - Assignees: Imagination Technologies Limited - Applicants: Imagination Technologies Limited - Inventors: Ashish Darbari - Web page: https://patentgrep.com/patent/US9519611B2 ## CPC - G06F 9/466: {Transaction processing} - G06F 5/00: Methods or arrangements for data conversion without changing the order or content of the data handled - G06F 11/0745: {in an input/output transactions management context (input/output processing in general G06F13/00)} - G06F 11/0751: {Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06)} - G06F 11/079: {Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36)} - G06F 11/28: by checking the correct order of processing (G06F11/08 - G06F11/26 take precedence; monitoring patterns of pulse trains H03K5/19) - G06F 11/30: Monitoring - G06F 13/36: for access to common bus or bus system - G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design using a counter and an indexed table. The data structure includes a counter that keeps track of the number of in-flight transactions; a table that keeps track of the age of each of the in-flight transactions using the counter; and control logic that verifies a transaction response has been received in the correct order (e.g. corresponds to the oldest in-flight transaction) based on the age information in the table. ## Claims ### Claim 1 A hardware data structure configured to track a plurality of ordered transactions in a multi-transactional hardware design, the hardware data structure comprising: a counter configured to store a value that tracks a number of in-flight transactions in the hardware design; a table configured to track an age of each of the in-flight transactions using the counter; and control logic configured to verify that a transaction response issued by the hardware design has been issued in a predetermined order based on the tracked ages of the in-flight transactions in the table. ### Claim 2 (depends on 1) The hardware data structure of claim 1, wherein verifying that the transaction response has been issued in the predetermined order comprises verifying that the transaction response corresponds to the oldest in-flight transaction based on the tracked ages of the in-flight transactions in the table. ### Claim 3 (depends on 1) The hardware data structure of claim 1, wherein the table comprises an entry for each transaction of the plurality of ordered transactions, each entry comprising information indicating the age of the transaction when the transaction is an in-flight transaction. ### Claim 4 (depends on 3) The hardware data structure of claim 3, wherein each entry further comprises information indicating whether the transaction is currently in-flight. ### Claim 5 (depends on 4) The hardware data structure of claim 4, wherein the control logic comprises a request detection module configured to detect when a new transaction is in-flight by monitoring one or more control signals of an interface of the hardware design. ### Claim 6 (depends on 5) The hardware data structure of claim 5, wherein the control logic further comprises a counter control module, the counter control module configured, in response to the request detection module detecting that a new transaction is in-flight, to increment the counter value. ### Claim 7 (depends on 5) The hardware data structure of claim 5, wherein the control logic further comprises a table control module configured, in response to the request detection module detecting that a new transaction is in-flight, to update the entry of the table corresponding to the new in-flight transaction so that the information indicating the age of the new in-flight transaction is set to the counter value. ### Claim 8 (depends on 7) The hardware data structure of claim 7, wherein the table control module is further configured, in response to the request detection module detecting that a new transaction is in-flight, to update the entry of the table corresponding to the new in-flight transaction so that the information indicating whether the transaction is in-flight indicates the transaction is in-flight. ### Claim 9 (depends on 4) The hardware data structure of claim 4, wherein the control logic comprises a response detection module configured to detect when a transaction response has been issued by monitoring one or more control signals of an interface of the hardware design. ### Claim 10 (depends on 9) The hardware data structure of claim 9, wherein the control logic further comprises a counter control module configured, in response to the response detection module detecting that a transaction response has been issued, to decrement the counter value. ### Claim 11 (depends on 9) The hardware data structure of claim 9, wherein the control logic further comprises a table control module configured, in response to the response detection module detecting that a transaction response has been issued, to update the entry of the table corresponding to the transaction response so that the information indicating whether the transaction is in-flight indicates the transaction is not in-flight. ### Claim 12 (depends on 11) The hardware data structure of claim 11, wherein the table control module is further configured, in response to the response detection module detecting that a transaction response has been issued, to decrement the information indicating the age of the transaction in the table for each in-flight transaction. ### Claim 13 (depends on 9) The hardware data structure of claim 9, wherein the control logic further comprises an error detection module configured, in response to the response detection module detecting that a transaction response has been issued, to verify that the transaction response has been issued in the predetermined order based on the information indicating the age of the transaction of the entry of the table corresponding to the transaction response. ### Claim 14 (depends on 13) The hardware data structure of claim 13, wherein the error detection module is configured to verify that the transaction response has been issued in the predetermined order using one or more assertions written in an assertion-based language. ### Claim 15 (depends on 14) The hardware data structure of claim 14, wherein the error detection module verifies that the transaction response has been issued in the predetermined order by evaluating the one or more assertions for one or more states of the hardware design. ### Claim 16 (depends on 14) The hardware data structure of claim 14, wherein the error detection module verifies that the transaction response has been issued in the predetermined order by evaluating the one or more assertions as input stimuli are applied to the hardware design. ### Claim 17 (depends on 14) The hardware data structure of claim 14, wherein the error detection module is configured to verify that the transaction response has been issued in the predetermined order using one or more assertions under one or more fairness constraints. ### Claim 18 (depends on 3) The hardware data structure of claim 3, wherein each transaction comprises a transaction ID and the entry of the table corresponding to a particular transaction is identified by the transaction ID. ### Claim 19 A method of tracking a plurality of ordered transactions in a multi-transactional hardware design, the method comprising: tracking a number of in-flight transactions in the hardware design using a counter; tracking an age of each of the in-flight transactions in a table using the counter; and verifying that a transaction response issued by the hardware design has been issued in a predetermined order based on the tracked ages of the in-flight transactions in the table. ### Claim 20 A non-transitory computer readable storage medium having stored thereon computer executable instructions that when executed cause at least one processor to: track a number of in-flight transactions in a multi-transactional hardware design using a counter; track an age of each of the in-flight transactions in a table using the counter; and verify that a transaction response issued by the multi-transactional hardware design has been issued in a predetermined order based on the tracked ages of the in-flight transactions in the table.