# US 9,519,609 B2 · On-package input/output architecture

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- Number: US 9,519,609 B2
- Document ID: US9519609B2
- Status: Granted
- Kind: B2
- Application number: 13/995,007
- Filed: 2011-12-22
- Published: 2013-11-28
- Granted: 2016-12-13
- Earliest claimed: 2011-12-22
- Assignees: Intel Corporation
- Applicants: Thomas P. Thomas; Rajesh Kumar
- Inventors: Thomas P. Thomas; Rajesh Kumar
- Web page: https://patentgrep.com/patent/US9519609B2

## CPC

- G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)}
- G06F 13/40: Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)}
- G06F 13/4086: {Bus impedance matching, e.g. termination}
- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

## Claims

### Claim 1

An apparatus comprising:
a first set of single-ended transmitter circuits on a first die having input/outputs (I/Os), the first die within a semiconductor package, wherein the transmitter circuits are impedance matched and have no equalization;
a first set of single-ended receiver circuits on a second die having I/Os, the second die within the semiconductor package, wherein the receiver circuits have no termination and no equalization; and
a plurality of conductive lines disposed on a planar board that are each directly coupled to both the I/Os of first die and the I/Os of the second die to directly couple the first set of transmitter circuits and the first set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched, and wherein the I/Os of the first die and the I/Os of the second die couple to the planar board beneath the first die and second die respectively and are not pins that couple into sockets.

### Claim 2 (depends on 1)

The apparatus of claim 1 further comprising:
a second set of single-ended receiver circuits on the first die, wherein the second set of single-ended receiver circuits have no termination and no equalization;
a second set of single-ended transmitter circuits on the second die, wherein the second set of transmitter circuits are impedance matched and have no equalization; and
a plurality of conductive lines between the second set of transmitter circuits and the second set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the first die comprises at least a processor core, the apparatus further comprising a touch screen interface coupled with the processor core.

### Claim 4 (depends on 1)

The apparatus of claim 1 wherein a gap between the first die and the second die is less than 20 mm.

### Claim 5 (depends on 4)

The apparatus of claim 4 wherein the gap is equal to or less than 1.5 mm.

### Claim 6

A tablet computing device comprising:
a touch screen interface;
a first set of single-ended transmitter circuits on a first die, the first die within a semiconductor package, wherein the transmitter circuits are impedance matched and have no equalization;
a first set of single-ended receiver circuits on a second die, the second die within a semiconductor package, wherein the receiver circuits have no termination and no equalization; and
a plurality of conductive lines disposed on a planar board that are each directly coupled to both the I/Os of first die and the I/Os of the second die to directly couple the first set of transmitter circuits and the first set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched, and wherein the I/Os of the first die and the I/Os of the second die couple to the planar board beneath the first die and second die respectively and are not pins that couple into sockets.

### Claim 7 (depends on 6)

The tablet of claim 6 further comprising:
a second set of single-ended receiver circuits on the first die, wherein the second set of single-ended receiver circuits have no termination and no equalization;
a second set of single-ended transmitter circuits on the second die, wherein the second set of single-ended transmitter circuits are impedance matched and have no equalization; and
a plurality of conductive lines between the second set of transmitter circuits and the second set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched.

### Claim 8 (depends on 6)

The tablet of claim 6 further comprising an antenna for communication.

### Claim 9 (depends on 6)

The tablet of claim 6 wherein a gap between the first die and the second die is less than 20 mm.

### Claim 10 (depends on 9)

The tablet of claim 9 wherein the gap is equal to or less than 1.5 mm.

### Claim 11

A system comprising:
an omnidirectional antenna;
a first set of single-ended transmitter circuits on a first die, the first die within a semiconductor package, wherein the transmitter circuits are impedance matched and have no equalization;
a first set of single-ended receiver circuits on a second die, the second die within the semiconductor package, wherein the receiver circuits have no termination and no equalization; and
a plurality of conductive lines disposed on a planar board that are each directly coupled to both the I/Os of first die and the I/Os of the second die to directly couple the first set of transmitter circuits and the first set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched, and wherein the I/Os of the first die and the I/Os of the second die couple to the planar board beneath the first die and second die respectively and are not pins that couple into sockets.

### Claim 12 (depends on 11)

The system of claim 11 further comprising:
a second set of single-ended receiver circuits on the first die, wherein the second set of single-ended receiver circuits have no termination and no equalization;
a second set of single-ended transmitter circuits on the second die, wherein the second set of single-ended transmitter circuits are impedance matched and have no equalization; and
a plurality of conductive lines between the second set of transmitter circuits and the second set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched.

### Claim 13 (depends on 11)

The system of claim 11, wherein the first die comprises at least a processor core, the apparatus further comprising a touch screen interface coupled with the processor core.

### Claim 14 (depends on 11)

The system of claim 11 wherein a gap between the first die and the second die is less than 20 mm.

### Claim 15 (depends on 14)

The system of claim 14 wherein the gap is equal to or less than 1.5 mm.