# US 9,519,583 B1 · Dedicated memory structure holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,519,583 B1 - Document ID: US9519583B1 - Status: Granted - Kind: B1 - Application number: 14/963,918 - Filed: 2015-12-09 - Granted: 2016-12-13 - Earliest claimed: 2015-12-09 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: George L. Chiu; Alexandre E. Eichenberger; John K. P. O'Brien - Web page: https://patentgrep.com/patent/US9519583B1 ## CPC - G06F 12/0811: with multilevel cache hierarchies - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 9/544: {Buffers; Shared memory; Pipes} - G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories} - G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding} - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F 9/5016: {the resource being the memory} - G06F 9/52: Program synchronisation; Mutual exclusion, e.g. by means of semaphores - G06F 2209/5018: Thread allocation - G06F 2212/283: Plural cache memories - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure relates generally to a dedicated memory structure (that is, hardware device) holding data for detecting available worker thread(s) and informing available worker thread(s) of task(s) to execute. ## Claims ### Claim 1 A computer system, the computer system comprising: a first processor comprising hardware; a first main memory associated with the first processor; a first L1 cache associated with the first processor; a first L2 cache associated with the first processor; a second processor comprising hardware; a second main memory associated with the second processor; a second L1 cache associated with the second processor; a second L2 cache associated with the second processor; and a dedicated memory structure for holding data indicating a plurality of available worker threads, the dedicated memory structure being distinct from each of the first main memory, the first L1 cache, the first L2 cache, the second main memory, the second L1 cache and the second L2 cache; wherein the first processor is configured to access, in the dedicated memory structure, the data, wherein the first processor is configured to detect from the data at least one first available worker thread, and wherein the first processor is configured to inform the detected at least one first available worker thread of at least one first task to execute and wherein the second processor is configured to access, in the dedicated memory structure, the data, wherein the second processor is configured to detect from the data at least one second available worker thread, and wherein the second processor is configured to inform the detected at least one second available worker thread of at least one second task to execute. ### Claim 2 (depends on 1) The computer system of claim 1, wherein: the data stored in the dedicated memory structure is for detecting by the first processor a first plurality of available worker threads and informing by the first processor each of the first plurality of detected available worker threads of the at least one first task to execute; and the data stored in the dedicated memory structure is for detecting by the second processor a second plurality of available worker threads and informing by the second processor each of the second plurality of detected available worker threads of the at least one second task to execute. ### Claim 3 (depends on 2) The computer system of claim 2, wherein: the data stored in the dedicated memory structure is for detecting by the first processor the first plurality of available worker threads and informing by the first processor each of the first plurality of detected available worker threads of a first plurality of tasks to execute; and the data stored in the dedicated memory structure is for detecting by the second processor the second plurality of available worker threads and informing by the second processor each of the second plurality of detected available worker threads of a second plurality of tasks to execute. ### Claim 4 (depends on 1) The computer system of claim 1, wherein: the first main memory comprises a first RAM; the first RAM is disposed externally to the first processor; the second main memory comprises a second RAM; and the second RAM is disposed externally to the second processor. ### Claim 5 (depends on 1) The computer system of claim 1, wherein: the first L1 cache is disposed on the first processor; the first L2 cache is disposed on the first processor; the second L1 cache is disposed on the second processor; and the second L2 cache is disposed on the second processor. ### Claim 6 (depends on 1) The computer system of claim 1, wherein the dedicated memory structure comprises an SRAM, the SRAM is disposed externally to the first processor and the SRAM is disposed externally to the second processor. ### Claim 7 A computer readable storage medium, tangibly embodying program instructions executable by a first computer processor and a second computer processor for storing and accessing data, the program instructions, when executing, performing the following steps: providing access, for the first computer processor, to a first main memory associated with the first computer processor; providing access, for the first computer processor, to a first L1 cache associated with the first computer processor; providing access, for the first computer processor, to a first L2 cache associated with the first computer processor; providing access, for the second computer processor, to a second main memory associated with the second computer processor; providing access, for the second computer processor, to a second L1 cache associated with the second computer processor; providing access, for the second computer processor, to a second L2 cache associated with the second computer processor; providing access, for the first computer processor, to a dedicated memory structure for holding data indicating a plurality of available worker threads, the dedicated memory structure being distinct from each of the first main memory, the first L1 cache, the first L2 cache, the second main memory, the second L1 cache and the second the L2 cache; providing access, for the second computer processor, to the dedicated memory structure; storing by the first computer processor, in the dedicated memory structure, at least some of the data; storing by the second computer processor, in the dedicated memory structure, at least some of the data; detecting by the first computer processor from the data stored in the dedicated memory structure at least one first available worker thread; detecting by the second computer processor from the data stored in the dedicated memory structure at least one second available worker thread; informing by the first computer processor the detected at least one first available worker thread of at least one first task to execute; and informing by the second computer processor the detected at least one second available worker thread of at least one second task to execute. ### Claim 8 (depends on 7) The storage medium of claim 7, wherein: the data stored in the dedicated memory structure is for detecting by the first processor a first plurality of available worker threads and informing by the first processor each of the first plurality of detected available worker threads of the at least one first task to execute; and the data stored in the dedicated memory structure is for detecting by the second processor a second plurality of available worker threads and informing by the second processor each of the second plurality of detected available worker threads of the at least one second task to execute. ### Claim 9 (depends on 6) The storage medium of claim 6, wherein: the data stored in the dedicated memory structure is for detecting by the first processor the first plurality of available worker threads and informing by the first processor each of the first plurality of detected available worker threads of a first plurality of tasks to execute; and the data stored in the dedicated memory structure is for detecting by the second processor the second plurality of available worker threads and informing by the second processor each of the second plurality of detected available worker threads of a second plurality of tasks to execute. ### Claim 10 (depends on 7) The storage medium of claim 7, wherein the first main memory comprises a first RAM and the second main memory comprises a second RAM. ### Claim 11 (depends on 10) The storage medium of claim 10, wherein the first RAM is disposed externally to the first computer processor and the second RAM is disposed externally to the second computer processor. ### Claim 12 (depends on 7) The storage medium of claim 7, wherein the first L1 cache is disposed on the first computer processor, wherein the first L2 cache is disposed on the first computer processor, wherein the second L1 cache is disposed on the second computer processor, and wherein the second L2 cache is disposed on the second computer processor. ### Claim 13 (depends on 7) The storage medium of claim 7, wherein the dedicated memory structure comprises an SRAM. ### Claim 14 A computer-implemented method for storing and accessing data, the method comprising: providing access, for a first computer processor, to a first main memory associated with the first computer processor; providing access, for the first computer processor, to a first L1 cache associated with the first computer processor; providing access, for the first computer processor, to a first L2 cache associated with the first computer processor; providing access, for a second computer processor, to a second main memory associated with the second computer processor; providing access, for the second computer processor, to a second L1 cache associated with the second computer processor; providing access, for the second computer processor, to a second L2 cache associated with the second computer processor, providing access, for the first computer processor, to a dedicated memory structure for holding data indicating a plurality of available worker threads, the dedicated memory structure being distinct from each of the first main memory, the first L1 cache, the first L2 cache, the second main memory, the second L1 cache and the second the L2 cache; providing access, for the second computer processor, to the dedicated memory structure; storing by the first computer processor, in the dedicated memory structure, at least some of the data; storing by the second computer processor, in the dedicated memory structure, at least some of the data; detecting by the first computer processor from the data stored in the dedicated memory structure at least one first available worker thread; detecting by the second computer processor from the data stored in the dedicated memory structure at least one second available worker thread; informing by the first computer processor the detected at least one first available worker thread of at least one first task to execute; and informing by the second computer processor the detected at least one second available worker thread of at least one second task to execute.