# US 9,519,582 B2 · Sense operation flags in a memory device

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- Number: US 9,519,582 B2
- Document ID: US9519582B2
- Status: Granted
- Kind: B2
- Application number: 14/833,175
- Filed: 2015-08-24
- Published: 2015-12-17
- Granted: 2016-12-13
- Earliest claimed: 2010-11-09
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Shafqat Ahmed; Khaled Hasnat; Pranav Kalavade; Krishna Parat; Aaron Yip; Mark A. Helm; Andrew Bicksler
- Web page: https://patentgrep.com/patent/US9519582B2

## CPC

- G06F 3/0625: {Power saving in storage systems}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0665: {at area level, e.g. provisioning of virtual or logical volumes}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 3/0689: {Disk arrays, e.g. RAID, JBOD}
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G06F 2212/2022: Flash memory
- G06F 2212/224: Disk storage
- G06F 2212/461: Sector or disk block
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

## Claims

### Claim 1

A memory device comprising:
a memory cell array comprising a main memory cell array and a flag memory cell array; and
a data cache coupled to the memory cell array, the data cache configured to store data to be programmed to and read from the main memory cell array and the flag memory cell array;
wherein a first main memory cell data line and a second main memory cell data line are configured to be selectively coupled to the data cache, wherein a first flag cell memory array data line is fixably coupled to the data cache, and wherein a second flag cell memory array data line is not coupled to the data cache.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the data cache comprises a plurality of data caches.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the plurality of data caches comprise a temporary data cache, a first dynamic data cache, a second dynamic data cache, a primary data cache, and a secondary data cache.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein the data cache further comprises a precharge circuit that is configured to precharge the data lines.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein the secondary data cache is coupled to an input/output connection of the memory device.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the first main memory cell data line is an odd main memory cell data line, the second main memory cell data line is an even main memory cell data line, the first flag cell memory array data line is an odd flag cell memory array data line, and the second flag cell memory array data line is an even flag cell memory array data line.

### Claim 7 (depends on 1)

The memory device of claim 1, further comprising multiplexing circuitry wherein the multiplexing circuitry comprises a respective select gate for each of the data lines, wherein the first flag cell memory array data line bypasses the respective select gate therefore and connects directly to a sense amplifier and the second flag cell memory array data line is disconnected across the respective select gate therefore.

### Claim 8 (depends on 1)

The memory device of claim 1, further comprising multiplexing circuitry and wherein the multiplexing circuitry comprises a respective helper gate for each of the data lines.

### Claim 9 (depends on 8)

The memory device of claim 8 wherein a helper gate for the first flag cell memory array data line is disconnected from the first flag cell memory array data line and a helper gate for the second flag cell memory array data line is shorted to the second flag cell memory array data line.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein there is an open circuit between the second flag cell memory array data line and the data cache.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein the first flag cell memory array data line fixably coupled to the data cache is shorted to the data cache.

### Claim 12

A memory device comprising:
a memory array comprising a main memory cell array and a flag memory cell array;
a dynamic data cache coupled to the memory array and configured to store data read from the memory array and data to be programmed to the memory array;
multiplexing circuitry that couples the dynamic data cache to the memory array, the multiplexing circuitry configured to selectively multiplex first data lines and second data lines of the main memory cell array to the dynamic data cache, disconnect first data lines of the flag memory cell array from the dynamic data cache, and short second data lines of the flag memory cell array to the dynamic data cache; and
memory control circuitry configured to control operation of the memory device.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the memory control circuitry is configured to simultaneously sense the first data lines of the main memory cell array and the second data lines of the flag memory cell array.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein memory cells in the flag memory cell array coupled to the second data lines of the flag memory cell array simultaneously sensed with the first data lines of the main memory cell array are configured to store flag data that indicates whether memory cells in the first memory array coupled to the first data lines of the main memory cell array are programmed.

### Claim 15 (depends on 12)

The memory device of claim 12, further comprising an access transistor configured to selectively couple the dynamic data cache to the multiplexing circuitry.

### Claim 16 (depends on 12)

The memory device of claim 12, wherein the multiplexing circuitry being configured to disconnect first data lines of the flag memory cell array from the dynamic data cache comprises the multiplexing circuitry being configured to fixably deselect the first data lines of the flag memory cell array.

### Claim 17

A memory device comprising:
a memory cell array comprising a main memory cell array and a flag memory cell array; and
a data cache coupled to the memory cell array, the data cache configured to store data to be programmed to and read from the main memory cell array and the flag memory cell array;
wherein first main memory cell data lines and second main memory cell data lines are configured to be selectively coupled to the data cache, wherein first flag cell memory array data lines are fixably coupled to the data cache, and wherein second flag cell memory array data lines are not coupled to the data cache; and
wherein flag memory cells in the flag memory cell array coupled to the first flag cell memory array data lines are configured to store flag data that indicates whether memory cells in the main memory cell array coupled to the first main memory cell data lines are programmed.

### Claim 18 (depends on 17)

The memory device of claim 17, wherein the memory device is configured to sense the second main memory cell data lines and the first flag cell memory array data lines, wherein the memory device is configured to re-sense the second main memory cell data lines when the flag data indicates that the memory cells in the main memory cell array coupled to the first main memory cell data lines are programmed.

### Claim 19 (depends on 17)

The memory device of claim 17, wherein the memory device is configured to change a sense voltage applied to the memory cells in the main memory cell array coupled to the first main memory cell data lines, memory cells in the main memory cell array coupled to the second main memory cell data lines, and the flag memory cells in the flag memory cell array coupled to the first flag cell memory array data lines when the flag data indicates that the memory cells in the main memory cell array coupled to the first main memory cell data lines are programmed.

### Claim 20 (depends on 19)

The memory device of claim 19, wherein the memory cells in the main memory cell array coupled to the first main memory cell data lines are adjacent to the memory cells in the main memory cell array coupled to the second main memory cell data lines.

### Claim 21 (depends on 17)

The memory device of claim 17, wherein the memory cells in the main memory cell array coupled to the first main memory cell data lines comprise a first page of memory cells and memory cells in the main memory cell array coupled to the second main memory cell data lines comprise a second page of memory cells.