# US 9,519,546 B2 · Striping cache blocks with logical block address scrambling

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- Number: US 9,519,546 B2
- Document ID: US9519546B2
- Status: Granted
- Kind: B2
- Application number: 14/215,637
- Filed: 2014-03-17
- Published: 2015-09-17
- Granted: 2016-12-13
- Earliest claimed: 2014-03-17
- Assignees: Dell Products L.P.
- Applicants: Dell Products L.P.
- Inventors: Scott Peterson; Phillip Krueger
- Web page: https://patentgrep.com/patent/US9519546B2

## CPC

- G06F 11/1446: Point-in-time backing up or restoration of persistent data
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 11/1666: {where the redundant component is memory or memory area}
- G06F 11/2058: {using more than 2 mirrored copies}
- G06F 11/2069: {Management of state, configuration or failover}
- G06F 11/2097: {maintaining the standby controller/processing unit updated (initialisation or re-synchronisation thereof G06F11/1658 and subgroups)}
- G06F 12/0813: with a network or matrix configuration
- G06F 12/084: with a shared cache
- G06F 12/0871: Allocation or management of cache space
- G06F 11/1471: involving logging of persistent data for recovery
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 2201/80: Database-specific techniques
- G06F 2212/1016: Performance improvement
- G06F 2212/154: Networked environment
- G06F 2212/214: Solid state disk
- G06F 2212/261: Storage comprising a plurality of storage devices
- G06F 2212/284: being distributed
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7207: management of metadata or control data
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for information handling systems includes receiving a storage operation to be applied to a cache block in a location in a distributed storage system. The location is defined by a logical block address (LBA). The method further includes swapping a first portion of the LBA with a second portion of the LBA, resulting in a modified LBA, and performing the storage operation with the modified LBA. The first portion and the second portion are both x bits wide.

## Claims

### Claim 1

A method for information handling systems, comprising:
receiving a storage operation to be applied to a cache block in a location in a distributed storage system, the location defined by a logical block address (LBA);
swapping a first portion of the LBA that includes the highest x bits of an offset definition with a second portion of the LBA, wherein the first portion and the second portion are both x bits wide, resulting in a modified LBA; and
performing the storage operation with the modified LBA.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second portion of the LBA is from a cache block identifier in the LBA.

### Claim 3 (depends on 2)

The method of claim 2, wherein the second portion includes the lowest x bits of the cache block identifier in the LBA.

### Claim 4 (depends on 1)

The method of claim 1, wherein swapping the first portion of the second portion causes the modified LBA to indicate a different offset and a different cache block identifier than the LBA.

### Claim 5 (depends on 1)

The method of claim 1, wherein memories used to implement the distributed storage system include flash devices of different sizes.

### Claim 6 (depends on 1)

The method of claim 1:
wherein upon a failure of a node within the distributed storage system, the results of the storage operation are persistently stored in one or more attached memory devices and are available for client access; and
further comprising, after the failure of the node within the distributed storage system:
providing read and write access for clients to the results of the storage operation; and
replicating the results of the storage operation to another location within the distributed storage system.

### Claim 7 (depends on 1)

The method of claim 1, further comprising concurrently allowing a first access and a second access to a logical unit including the results of the storage operation, the first access and the second access each including a read or write operation.

### Claim 8 (depends on 1)

The method of claim 1, wherein:
the cache block is included in a plurality of cache blocks of a logical unit; and
the method further comprises provisioning the logical unit without use of auxiliary storage for flushing.

### Claim 9 (depends on 1)

The method of claim 1, wherein:
the cache block is implemented in a first attached memory;
the distributed storage system comprises a second cache block implemented in a second cache memory; and
the method further comprises adding or removing the second cache memory while the storage operation is received and performed.

### Claim 10

An article of manufacture, comprising:
a non-transitory machine-readable medium; and
instructions on the computer-readable medium, when read by a processor, are configured to cause the processor to:
receive a storage operation to be applied to a cache block in a location in a distributed storage system, the location defined by a logical block address (LBA);
swap a first portion of the LBA that includes the highest x bits of an offset definition with a second portion of the LBA, wherein the first portion and the second portion are both x bits wide, resulting in a modified LBA; and
perform the storage operation with the modified LBA.

### Claim 11 (depends on 10)

The article of claim 10, wherein the second portion of the LBA is from a cache block identifier in the LBA.

### Claim 12 (depends on 11)

The article of claim 11, wherein the second portion includes the lowest x bits of the cache block identifier in the LBA.

### Claim 13 (depends on 10)

The article of claim 10, wherein swapping the first portion of the second portion causes the modified LBA to indicate a different offset and a different cache block identifier than the LBA.

### Claim 14 (depends on 10)

The article of claim 10, wherein memories used to implement the distributed storage system include flash devices of different sizes.

### Claim 15 (depends on 10)

The article of claim 10:
wherein upon a failure of a node within the distributed storage system, the results of the storage operation are persistently stored in one or more attached memory devices and are available for client access; and
the processor is further configured to, after the failure of the node within the distributed storage system:
provide read and write access for clients to the results of the storage operation; and
replicate the results of the storage operation to another location within the distributed storage system.

### Claim 16 (depends on 10)

The article of claim 10, wherein the processor is further configured to concurrently allow a first access and a second access to a logical unit including the results of the storage operation, the first access and the second access each including a read or write operation.

### Claim 17 (depends on 10)

The article of claim 10, wherein:
the cache block is included in a plurality of cache blocks of a logical unit; and
the processor is further configured to provision the logical unit without use of auxiliary storage for flushing.

### Claim 18 (depends on 10)

The article of claim 10, wherein:
the cache block is implemented in a first attached memory;
the distributed storage system comprises a second cache block implemented in a second cache memory; and
the processor is further configured to add or remove the second cache memory while the storage operation is received and performed.

### Claim 19

An information handling system, comprising:
a processor;
a machine-readable medium comprising instructions, when read and executed by the processor, are configured to cause the processor to:
receive a storage operation to be applied to a cache block in a location in a distributed storage system, the location defined by a logical block address (LBA);
swap a first portion of the LBA that includes the highest x bits of an offset definition with a second portion of the LBA, wherein the first portion and the second portion are both x bits wide, resulting in a modified LBA; and
perform the storage operation with the modified LBA.

### Claim 20 (depends on 19)

The information handling system of claim 19, wherein the second portion of the LBA is from a cache block identifier in the LBA.

### Claim 21 (depends on 20)

The information handling system of claim 20, wherein the second portion includes the lowest x bits of the cache block identifier in the LBA.

### Claim 22 (depends on 19)

The information handling system of claim 19, wherein swapping the first portion of the second portion causes the modified LBA to indicate a different offset and a different cache block identifier than the LBA.

### Claim 23 (depends on 19)

The information handling system of claim 19:
wherein upon a failure of a node within the distributed storage system, the results of the storage operation are persistently stored in one or more attached memory devices and are available for client access; and
the processor is further configured to, after the failure of the node within the distributed storage system:
provide read and write access for clients to the results of the storage operation; and
replicate the results of the storage operation to another location within the distributed storage system.

### Claim 24 (depends on 19)

The information handling system of claim 19, wherein the processor is further configured to concurrently allow a first access and a second access to a logical unit including the results of the storage operation, the first access and the second access each including a read or write operation.

### Claim 25 (depends on 19)

The information handling system of claim 19, wherein:
the cache block is included in a plurality of cache blocks of a logical unit; and
the processor is further configured to provision the logical unit without use of auxiliary storage for flushing.

### Claim 26 (depends on 19)

The information handling system of claim 19, wherein:
the cache block is implemented in a first attached memory;
the distributed storage system comprises a second cache block implemented in a second cache memory; and
the processor is further configured to add or remove the second cache memory while the storage operation is received and performed.