# US 9,519,541 B2 · Data storage device and data checking and correction for volatile memory

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- Number: US 9,519,541 B2
- Document ID: US9519541B2
- Status: Granted
- Kind: B2
- Application number: 14/271,813
- Filed: 2014-05-07
- Published: 2015-08-13
- Granted: 2016-12-13
- Earliest claimed: 2014-02-08
- Assignees: VIA Technologies, Inc.
- Applicants: Via Technologies, Inc.
- Inventors: Lei Feng
- Web page: https://patentgrep.com/patent/US9519541B2

## CPC

- G06F 11/108: {Parity data distribution in semiconductor storages, e.g. in SSD}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 2211/109: Sector level checksum or ECC, i.e. sector or stripe level checksum or ECC in addition to the RAID parity calculation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Data checking and correction for a volatile memory of a data storage device, the data storage device further including a non-volatile memory and a controller. The controller operates the non-volatile memory in accordance with requests issued from a host. The controller uses the volatile memory for temporary storage of temporary data required for operations of the non-volatile memory. The controller generates error checking and correction content for the temporary data and writes the temporary data and the error checking and correction content into the volatile memory in at least one burst length for temporary storage of the temporary data. In this manner, it is not necessary to manufacture any additional pin on the volatile memory for data checking and correction.

## Claims

### Claim 1

A data storage device, comprising:
a non-volatile memory;
a volatile memory; and
a controller, operating the non-volatile memory in accordance with requests issued from a host and using the volatile memory for temporary storage of temporary data for operations of the non-volatile memory,
wherein:
the controller generates error checking and correction content for the temporary data and writes the temporary data and the error checking and correction content into the volatile memory in format of at least one burst length for temporary storage of the temporary data,
wherein the controller writes the temporary data into the volatile memory for temporary storage in format of a plurality of burst lengths;
the controller generates one error checking and correction word for each burst length of temporary data and combines the generated error checking and correction words to form the error checking and correction content; and
the controller writes the error checking and correction content into the volatile memory in format of one burst length after writing the temporary data into the volatile memory for temporary storage in format of the plurality of burst lengths.

### Claim 2 (depends on 1)

The data storage device as claimed in claim 1, wherein the controller is coupled to the volatile memory via a data bus and the burst length is M times a bus width of the data bus, and M is larger than or equal to 2.

### Claim 3 (depends on 1)

The data storage device as claimed in claim 1, wherein the controller is coupled to the volatile memory via a data bus and the burst length is 16 bytes while a bus width of the data bus is 16 bits.

### Claim 4 (depends on 1)

The data storage device as claimed in claim 1, wherein:
the controller generates error checking and correction content corresponding to controller data of half the burst length and writes the controller data of half the burst length and the corresponding error checking and correction content into the volatile memory in format of one burst length for temporary storage of the controller data of half the burst length,
wherein the controller data is for calculations which are required when the non-volatile memory is operated by the host.

### Claim 5 (depends on 4)

The data storage device as claimed in claim 4, wherein:
the controller reads one burst length of data from the volatile memory which contains the controller data of half the burst length and the error checking and correction content corresponding to the controller data of half the burst length; and
the controller performs an error checking and correction process on the controller data of half the burst length based on the corresponding error checking and correction content.

### Claim 6 (depends on 1)

The data storage device as claimed in claim 1, wherein:
the controller further generates one error checking and correction parity bit for (N−1) bits of mapping-table data and writes the (N−1) bits of mapping-table data and the error checking and correction parity bit into the volatile memory for temporary storage of the (N−1) bits of mapping-table data.

### Claim 7 (depends on 6)

The data storage device as claimed in claim 6, wherein:
the controller further reads the error checking and correction parity bit and the corresponding (N−1) bits of mapping-table data from the volatile memory and performs an error checking and correction process on the (N−1) bits of mapping-table data based on the error checking and correction parity bit.

### Claim 8 (depends on 1)

The data storage device as claimed in claim 1, wherein:
after reading one burst length of error checking and correction content from the volatile memory, the controller further reads the volatile memory for burst lengths of user data temporarily stored in the volatile memory and corresponding to the burst length of error checking and correction content and performs an error checking and correction process on the burst lengths of user data based on the burst length of error checking and correction content.

### Claim 9

A data error checking and correction method for a volatile memory of a data storage device, comprising:
generating error checking and correction content for temporary data required for operations of a non-volatile memory of the data storage device; and
writing the temporary data and the error checking and correction content into the volatile memory in format of at least one burst length for temporary storage of the temporary data,
wherein:
one error checking and correction word is generated for each burst length of temporary data and the generated error checking and correction words are combined to form the error checking and correction content;
the temporary data is written into the volatile memory for temporary storage in format of a plurality of burst lengths; and
the error checking and correction content is written into the volatile memory in format of one burst length after the temporary data is written into the volatile memory for temporary storage in format of the plurality of burst lengths.

### Claim 10 (depends on 9)

The data error checking and correction method as claimed in claim 9, wherein the burst length is M times a bus width of a data bus of the volatile memory, and M is larger than or equal to 2.

### Claim 11 (depends on 9)

The data error checking and correction method as claimed in claim 9, wherein:
error checking and correction content corresponding to controller data of half the burst length is generated and combined with the controller data of half the burst length to form one burst length of data to be written into the volatile memory for temporary storage of the controller data of half the burst length,
wherein the controller data is for calculations which are required when the non-volatile memory is operated by the host.

### Claim 12 (depends on 11)

The data error checking and correction method as claimed in claim 11, further comprising:
reading one burst length of data from the volatile memory which contains the controller data of half the burst length and the error checking and correction content corresponding to the controller data of half the burst length; and
performing an error checking and correction process on the controller data of half the burst length based on the corresponding error checking and correction content.

### Claim 13 (depends on 9)

The data error checking and correction method as claimed in claim 9, further comprising:
generating one error checking and correction parity bit for (N−1) bits of mapping-table data; and
writing the (N−1) bits of mapping-table data and the error checking and correction parity bit into the volatile memory for temporary storage of the (N−1) bits of mapping-table data.

### Claim 14 (depends on 13)

The data error checking and correction method as claimed in claim 13, further comprising:
reading the error checking and correction parity bit and the corresponding (N−1) bits of mapping-table data from the volatile memory and performing an error checking and correction process on the (N−1) bits of mapping-table data based on the error checking and correction parity bit.

### Claim 15 (depends on 9)

The data error checking and correction method as claimed in claim 9, further comprising:
after reading one burst length of error checking and correction content from the volatile memory, further reading the volatile memory for burst lengths of user data temporarily stored in the volatile memory and corresponding to the burst length of error checking and correction content and performing an error checking and correction process on the burst lengths of user data based on the burst length of error checking and correction content.