# US 9,519,532 B2 · Handling system interrupts with long-running recovery actions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,519,532 B2 - Document ID: US9519532B2 - Status: Granted - Kind: B2 - Application number: 14/158,935 - Filed: 2014-01-20 - Published: 2015-07-23 - Granted: 2016-12-13 - Earliest claimed: 2014-01-20 - Assignees: Lenovo Enterprise Solutions (Singapore) Pte. Ltd. - Applicants: Lenovo Enterprise Solutions (Singapore) Pte. Ltd. - Inventors: Jonathan L. Kaus; Adam C. Lange-Pearson; Gary R. Ricard; Jaimeson Saley - Web page: https://patentgrep.com/patent/US9519532B2 ## CPC - G06F 11/0745: {in an input/output transactions management context (input/output processing in general G06F13/00)} - G06F 9/327: {for interrupts} - G06F 9/38: Concurrent instruction execution, e.g. pipeline or look ahead - G06F 11/0706: {the processing taking place on a specific hardware platform or in a specific software environment} - G06F 11/0721: {within a central processing unit [CPU]} - G06F 11/0784: {Routing of error reports, e.g. with a specific transmission path or data flow} - G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)} - G06F 13/24: using interrupt (G06F13/32 takes precedence) - G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers} - G06F 2201/81: Threshold - G06F 2211/002: Bus - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method, processor, and computer system for handling interrupts within a hierarchical register structure. The method includes receiving at a root-level register an indication of an interrupt occurring at a lower level register in the register structure, using a system interrupt handler to invoke an error handler assigned to a set of registers of the structure that includes the lower level register, and using the invoked error handler to handle the interrupt and return to the system interrupt handler. ## Claims ### Claim 1 A processor, comprising: a hierarchical interrupt register structure, comprising: a plurality of lower level registers, and a first root-level register configured to indicate an interrupt occurring at a first lower level register of the plurality of lower level registers; one or more error handlers, each error handler of the one or more error handlers assigned to a respective set of registers of the interrupt register structure; and a system interrupt handler configured to determine, based on a determined amount of time required to complete a prescribed recovery action for an interrupt, whether to directly handle the interrupt or to invoke an error handler of the one or more error handlers to handle the interrupt. ### Claim 2 (depends on 1) The processor of claim 1, wherein the system interrupt handler is further configured to, upon receiving an indication at the first root-level register of an interrupt occurring at one of the plurality of lower level registers: determine the lower level register that triggered the indication; and invoke a first error handler of the one or more error handlers, the first error handler assigned to a set of registers of the interrupt register structure that includes the determined lower level register. ### Claim 3 (depends on 1) The processor of claim 1, wherein the interrupt register structure further comprises at least a second root-level register, and wherein each of the first and second root-level registers is designated to indicate a respective class of interrupts. ### Claim 4 (depends on 3) The processor of claim 3, wherein the system interrupt handler is further configured to handle interrupts differently based on the indicated class of interrupts. ### Claim 5 (depends on 4) The processor of claim 4, wherein the classes of interrupts indicated by the first and second root-level registers includes one or more of recoverable errors, fatal errors, network interrupts, debug interrupts, and performance interrupts. ### Claim 6 (depends on 1) The processor of claim 1, wherein the one or more error handlers are configured to handle an interrupt asynchronously upon the system interrupt handler determining that execution of a recovery action for the interrupt would require an amount of time exceeding a predetermined threshold. ### Claim 7 (depends on 6) The processor of claim 6, wherein the one or more error handlers are further configured to: capture data required to handle the interrupt asynchronously; and instruct an asynchronous thread to execute the recovery action. ### Claim 8 A computer system, comprising: a processor, comprising: a hierarchical interrupt register structure, comprising: a plurality of lower level registers, and a first root-level register configured to indicate an interrupt occurring at a first lower level register of the plurality of lower level registers; one or more error handlers, each error handler of the one or more error handlers assigned to a respective set of registers of the interrupt register structure; and a system interrupt handler configured to determine, based on a determined amount of time required to complete a prescribed recovery action for an interrupt, whether to directly handle the interrupt or to invoke an error handler of the one or more error handlers to handle the interrupt. ### Claim 9 (depends on 8) The system of claim 8, wherein the system interrupt handler is further configured to, upon receiving an indication at the first root-level register of an interrupt occurring at one of the plurality of lower level registers: determine the lower level register that triggered the indication; and invoke a first error handler of the one or more error handlers, the first error handler assigned to a set of registers of the interrupt register structure that includes the determined lower level register. ### Claim 10 (depends on 8) The system of claim 8, wherein the interrupt register structure further comprises at least a second root-level register, and wherein each of the first and second root-level registers is designated to indicate a respective class of interrupts. ### Claim 11 (depends on 10) The system of claim 10, wherein the system interrupt handler is further configured to handle interrupts differently based on the indicated class of interrupts. ### Claim 12 (depends on 11) The system of claim 11, wherein the classes of interrupts indicated by the first and second root-level registers includes one or more of recoverable errors, fatal errors, network interrupts, debug interrupts, and performance interrupts. ### Claim 13 (depends on 8) The system of claim 8, wherein the one or more error handlers are configured to handle an interrupt asynchronously upon the system interrupt handler determining that execution of a recovery action for the interrupt would require an amount of time exceeding a predetermined threshold. ### Claim 14 (depends on 13) The system of claim 13, wherein the one or more error handlers are further configured to: capture data required to handle the interrupt asynchronously; and instruct an asynchronous thread to execute the recovery action. ### Claim 15 A method of handling interrupts in a processor comprising a hierarchical interrupt register structure, the method comprising: receiving, at a root-level register of the interrupt register structure, an indication of an interrupt occurring at a lower level register of the interrupt register structure; determining, at a system interrupt handler and based on a determined amount of time required to complete a prescribed recovery action for the interrupt, whether to directly handle the interrupt with the system interrupt handler or to invoke an error handler to handle the interrupt; and handling the interrupt based on the determination. ### Claim 16 (depends on 15) The method of claim 15, further comprising: determining the lower level register that triggered the indication; and selecting the error handler to be invoked from a plurality of error handlers, each error handler being assigned to a respective set of registers of the interrupt register structure, the selected error handler corresponding to a set of registers that includes the determined lower level register. ### Claim 17 (depends on 15) The method of claim 15, wherein handling the interrupt using the error handler is completed asynchronously upon determining that execution of a recovery action for the interrupt would require an amount of time exceeding a predetermined threshold. ### Claim 18 (depends on 17) The method of claim 17, further comprising: capturing, using the error handler, data required to handle the interrupt asynchronously; and instructing an asynchronous thread to execute the recovery action before returning execution to the system interrupt handler. ### Claim 19 (depends on 15) The method of claim 15, wherein the interrupt register structure comprises a plurality of root-level registers, and wherein each root-level register is designated to indicate a respective class of interrupts. ### Claim 20 (depends on 19) The method of claim 19, wherein the system interrupt handler is further configured to handle interrupts differently based on the indicated class of interrupts, and wherein the indicated class of interrupts includes one of recoverable errors, fatal errors, network interrupts, debug interrupts, and performance interrupts.