# US 9,519,488 B2 · External intrinsic interface > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,519,488 B2 - Document ID: US9519488B2 - Status: Granted - Kind: B2 - Application number: 13/398,305 - Filed: 2012-02-16 - Published: 2013-01-31 - Granted: 2016-12-13 - Earliest claimed: 2011-07-25 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Kwon Taek Kwon; Seok Yoon Jung - Inventors: Kwon Taek Kwon; Seok Yoon Jung - Web page: https://patentgrep.com/patent/US9519488B2 ## CPC - G06F 9/3881: {Arrangements for communication of instructions and data} - G06F 9/3869: {Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking} - G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)} - G06F 9/3885: {using a plurality of independent parallel functional units} - G06F 15/76: Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An external intrinsic interface. A processor may include a core including a plurality of functional units, an intrinsic module located outside the core, and an interface module to perform relaying between the intrinsic module and a functional unit, among the plurality of functional units. ## Claims ### Claim 1 A processor, comprising: a core comprising of functional units; an intrinsic module disposed outside the core; and an interface module to perform relaying between the intrinsic module and a functional unit among the functional units, such that stall cycle hiding is performed in response to a stall occurring in the core or the intrinsic module, and wherein whether the stall cycle hiding is performed by an output FIFO register or an input FIFO register is determined by which one of the core or the intrinsic module the stall occurs in, wherein in response to a stall occurring in the core, the interface module stalls the intrinsic module based on an available storage space in an output FIFO register, and wherein in response to a stall occurring in the intrinsic module, a control unit of the interface module stalls the core based on an available storage space in an input FIFO register. ### Claim 2 (depends on 1) The processor of claim 1, wherein the interface module comprises: the input first-in-first-out (FIFO) register; the output FIFO register; and the control unit. ### Claim 3 (depends on 2) The processor of claim 2, wherein, in response to a clock domain of the core differing from a clock domain of the intrinsic module, the control unit performs a clock domain crossing process, using the input FIFO register and the output FIFO register. ### Claim 4 (depends on 2) The processor of claim 2, wherein, in response to a stall occurring in the core, the control unit performs stall cycle hiding, using the output FIFO register. ### Claim 5 (depends on 4) The processor of claim 4, wherein, in response to there being an available storage space in the output FIFO register, the control unit stores, in the output FIFO register, a result value received from the intrinsic module. ### Claim 6 (depends on 2) The processor of claim 2, wherein, in response to a stall occurring in the intrinsic module, the control unit performs stall cycle hiding, using the input FIFO register. ### Claim 7 (depends on 6) The processor of claim 6, wherein, in response to there being an available storage space in the input FIFO register, the control unit stores, in the input FIFO register, a request received from the core. ### Claim 8 (depends on 1) The processor of claim 1, wherein the interface module receives an operation request from the functional unit, transfers the received operation request to the intrinsic module, receives a result value corresponding to the operation request from the intrinsic module, and transfers the received result value to the functional unit. ### Claim 9 (depends on 1) The processor of claim 1, wherein the intrinsic module is used as a load and/or store (LD/ST) intrinsic module, and the interface module performs an LD/ST operation of reading and writing a predetermined value with respect to the intrinsic module at an address given by an argument. ### Claim 10 (depends on 1) The processor of claim 1, wherein in response to a stall occurring in the core and an available storage space in an output FIFO register of the interface module, a control unit of the interface module continues to operate the intrinsic module without stalling the intrinsic module, and in response to a stall occurring in the core and the output FIFO register being without available storage space, the control unit of the interface module stalls the intrinsic module. ### Claim 11 (depends on 10) The processor of claim 10, wherein in response to the interface module stalling the intrinsic module, the interface module determines whether the core continues to be stalled, and in response to the control unit determining that the core continues to be stalled, the control unit determines whether the output FIFO register comprises the available storage space. ### Claim 12 (depends on 1) The processor of claim 1, wherein in response to a stall occurring in the intrinsic module and an available storage space in an input FIFO register of the interface module, a control unit of the interface module continues to operate the core without stalling the core, and in response to a stall occurring in the intrinsic module and the input FIFO register being without available storage space, the control unit of the interface module stalls the core. ### Claim 13 (depends on 12) The processor of claim 12, wherein in response to the intrinsic module stalling the core, the control unit determines whether the intrinsic module continues to be stalled, and in response to the control unit determining that the intrinsic module continues to be stalled, the control unit determines whether the input FIFO register comprises the available storage space. ### Claim 14 (depends on 1) The processor of claim 1, wherein, in response to a clock domain of the core differing from a clock domain of the intrinsic module, a control unit of the interface module performs a clock domain crossing process on the intrinsic module and the core in order to synchronize a clock frequency of the core with a clock frequency of the intrinsic module. ### Claim 15 (depends on 1) The processor of claim 1, wherein the interface module searches for an intrinsic module corresponding to an opcode received from the functional unit, and in response to finding the intrinsic module, performs relaying between the found intrinsic module and the functional unit. ### Claim 16 (depends on 1) The processor of claim 1, wherein in response to a difference in operation speed between the core and the intrinsic module, a control unit stores requests from the core in an input FIFO register and transfers the stored requests to the intrinsic module based on a speed that the intrinsic module receives the requests. ### Claim 17 (depends on 1) The processor of claim 1, wherein the control unit of the interface module is disposed directly between an input FIFO register and the output FIFO register, and the intrinsic module is disposed directly between the input FIFO register and the output FIFO register. ### Claim 18 (depends on 1) The processor of claim 1, wherein the output FIFO register is disposed downstream from the intrinsic module, the intrinsic module is disposed downstream from the input FIFO register, and the core is disposed downstream from the output FIFO register and upstream from the input FIFO register. ### Claim 19 A processor, comprising: a core comprising functional units; and an intrinsic module disposed outside the core and processing operation requests for the functional units, the processor being operated such that stall cycle hiding is performed in response to a stall occurring in the core or the intrinsic module, and wherein whether the stall cycle hiding is performed by an output FIFO register or an input FIFO register is determined by which one of the core or the intrinsic module the stall occurs in, wherein in response to a stall occurring in the core, a control unit stalls the intrinsic module based on an available storage space in an output FIFO register, and wherein in response to a stall occurring in the intrinsic module, the control unit stalls the core based on an available storage space in an input FIFO register.