# US 9,519,372 B2 · Gate driving circuit for time division driving, method thereof and display apparatus having the same

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- Number: US 9,519,372 B2
- Document ID: US9519372B2
- Status: Granted
- Kind: B2
- Application number: 14/369,525
- Filed: 2013-12-16
- Published: 2015-04-02
- Granted: 2016-12-13
- Earliest claimed: 2013-09-29
- Assignees: Boe Technology Group Co., Ltd.; Chengdu Boe Optoelectronics Technology Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Chengdu Boe Optoelectronics Technology Co., Ltd.
- Inventors: Xiangdan Dong; Young Yik Ko; Weiyun Huang
- Web page: https://patentgrep.com/patent/US9519372B2

## CPC

- G06F 3/0416: {Control or interface arrangements specially adapted for digitisers}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G06F 3/04184: {Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally}
- G09G 3/3674: {Details of drivers for scan electrodes}
- G09G 3/3677: {suitable for active matrices only}
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The present disclosure relates to the field of display technology, and provides a gate driving circuit, a gate line driving method and a display apparatus capable of solving the technical problem of display defects caused by the interrupt of the scan signal in the touch screen technology with time division driving. The gate driving circuit comprises multiple shift register units connected in series, and further comprises a shift delay module and a repeat output module, wherein the shift delay module is connected in series between the jth stage of shift register unit and the (j+1)th stage of shift register unit which are adjacent to each other; the shift delay module is connected to the output terminal of the jth stage of shift register unit and the input terminal of the (j+1)th stage of shift register unit, and the shift delay module is also connected to the repeat output module; the repeat output module is connected to the output terminal of the (j−n+1)th stage of shift register unit and a clock control terminal. Embodiments of the present disclosure can be applied to display manufacture.

## Claims

### Claim 1

A gate driving circuit comprising multiple shift register units connected in series, wherein it further comprises a shift delay module and a repeat output module, and the shift delay module is connected in series between the jth stage of shift register unit and the (j+1)th stage of shift register unit which are adjacent to each other wherein j is a positive integer;
the shift delay module is connected to the output terminal of the jth stage of shift register unit and the input terminal of the (j+1)th stage of shift register unit, and also connected to the repeat output module;
the repeat output module is connected to the output terminal of the (j−n+1)th stage of shift register unit and a clock control terminal, wherein n is a positive integer and n is equal to or less than j; and
after the jth stage of shift register unit outputs a gate scan signal, a clock signal is input from the clock control terminal to turn on the repeat output module after a preset touch time ends, such that the shift delay module outputs a repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit through the repeat output module, and each of the shift register units from the (j−n+1)th stage to the jth stage re-outputs a scan signal to a gate line in sequence.

### Claim 2 (depends on 1)

The gate driving circuit of claim 1, wherein the repeat output module is also connected to a reference voltage terminal, and the repeat output module is controlled by the voltage of the reference voltage terminal to stop outputting the repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit when the jth stage of shift register unit outputs repeatedly the scan signal.

### Claim 3 (depends on 2)

The gate driving circuit of claim 2, wherein the repeat output module comprises an output unit and a pull down unit;
the shift delay module comprises i virtual shift register units connected in series, wherein the input terminal of the first stage of virtual shift register unit is connected to the output terminal of the jth stage of shift register unit, the output terminal of the first stage of virtual shift register unit is connected to the output unit, the clock control terminal is connected to the output unit, the output terminal of the ith virtual shift register unit is connected to the pull down unit and the input terminal of the (j+1)th stage of shift register unit, where i=n;
the output unit is configured to output the repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit under the control of the clock control terminal; and
the pull down unit is also connected to the reference voltage terminal and an output control terminal of the first stage of virtual shift register unit, and is configured to control the first stage of virtual shift register unit by the voltage of the reference voltage terminal to stop outputting the repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit through the output unit.

### Claim 4 (depends on 3)

The gate driving circuit of claim 3, wherein the output unit comprises a first switch transistor whose gate is connected to the clock control terminal, whose source is connected to the shift delay module, and whose drain is connected to the output terminal of the jth stage of shift register unit; and
the pull down unit comprises a second switch transistor whose gate is connected to the output terminal of the nth stage of virtual shift register unit, whose source is connected to the reference voltage terminal, and whose drain is connected to the gate of a gate line driving signal output transistor in the first stage of virtual shift register unit.

### Claim 5 (depends on 2)

The gate driving circuit of claim 2, wherein the repeat output module comprises an output unit and a pull down unit;
the shift delay module comprises i virtual shift register units connected in series, wherein the input terminal of the first stage of virtual shift register unit is connected to the output terminal of the jth stage of shift register unit, the output terminal of the ith stage of virtual shift register unit is connected to the pull down unit and the input terminal of the (j+1)th stage of shift register unit, and the clock control terminal is connected to the output unit, where i=2;
the output unit is configured to output the repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit under the control of the clock control terminal, where n=1; and
the pull down unit is also connected to the reference voltage terminal and an output control terminal of the first stage of virtual shift register unit, and is configured to control the first stage of virtual shift register unit by the voltage of the reference voltage terminal to output a signal to the next stage of virtual shift register unit, so as to control the output terminal of the ith stage of virtual shift register unit to stop outputting the repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit through the output unit.

### Claim 6 (depends on 5)

The gate driving circuit of claim 5, wherein the output unit comprises a first switch transistor whose gate is connected to the clock control terminal, whose source is connected to the shift delay module, and whose drain is connected to the output terminal of the jth stage of shift register unit; and
the pull down unit comprises a second switch transistor whose gate is connected to the output terminal of the nth stage of virtual shift register unit, whose source is connected to the reference voltage terminal, and whose drain is connected to the gate of a gate line driving signal output transistor in the first stage of virtual shift register unit.

### Claim 7 (depends on 1)

The gate driving circuit of claim 1, wherein
the repeat output module is also connected to a reference voltage terminal and the output terminal of the (j+1)th stage of shift register unit, and is configured to control the repeat output module by the voltage of the reference voltage terminal to stop outputting the repeat scan signal to the output terminal of the jth stage of shift register unit when the (j+1)th stage of shift register unit outputs the scan signal.

### Claim 8 (depends on 7)

The gate driving circuit of claim 7, wherein the repeat output module comprises an output unit and a pull down unit;
the shift delay module comprises one first stage of virtual shift register unit, wherein the input terminal of the first stage of virtual shift register unit is connected to the output terminal of the jth stage of shift register unit, the output terminal of the first stage of virtual shift register unit is connected to the input terminal of the (j+1)th stage of shift register unit, and the output unit is connected to the clock control terminal;
the output unit is configured to output the repeat scan signal to the output terminal of the jth stage of shift register unit under the control of the clock control terminal; and
the pull down unit is also connected to the reference voltage terminal, the output terminal of the (j+1)th stage of shift register unit and an output control terminal of the first stage of virtual shift register unit, and is configured to control the first stage of virtual shift register unit by the voltage of the reference voltage terminal to stop outputting the repeat scan signal to the output terminal of the jth stage of shift register unit when the (j+1)th stage of shift register unit outputs the scan signal.

### Claim 9 (depends on 8)

The gate driving circuit of claim 8, wherein the output unit comprises a first switch transistor whose gate is connected to the clock control terminal, whose source is connected to the shift delay module, and whose drain is connected to the output terminal of the jth stage of shift register unit; and
the pull down unit comprises a second switch transistor whose gate is connected to the output terminal of the (j+1)th stage of shift register unit, whose source is connected to the reference voltage terminal, and whose drain is connected to the gate of a gate line driving signal output transistor in the first stage of virtual shift register unit.

### Claim 10 (depends on 1)

A display apparatus comprising the gate driving circuit according to claim 1.

### Claim 11 (depends on 10)

The display apparatus of claim 10, wherein
the repeat output module is also connected to a reference voltage terminal, and the repeat output module is controlled by the voltage of the reference voltage terminal to stop outputting the repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit when the jth stage of shift register unit outputs repeatedly the scan signal.

### Claim 12 (depends on 11)

The display apparatus of claim 11, wherein the repeat output module comprises an output unit and a pull down unit;
the shift delay module comprises i virtual shift register units connected in series, wherein the input terminal of the first stage of virtual shift register unit is connected to the output terminal of the jth stage of shift register unit, the output terminal of the first stage of virtual shift register unit is connected to the output unit, the clock control terminal is connected to the output unit, the output terminal of the ith virtual shift register unit is connected to the pull down unit and the input terminal of the (j+1)th stage of shift register unit, where i=n;
the output unit is configured to output the repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit under the control of the clock control terminal; and
the pull down unit is also connected to the reference voltage terminal and an output control terminal of the first stage of virtual shift register unit, and is configured to control the first stage of virtual shift register unit by the voltage of the reference voltage terminal to stop outputting the repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit through the output unit.

### Claim 13 (depends on 12)

The display apparatus of claim 12, wherein the output unit comprises a first switch transistor whose gate is connected to the clock control terminal, whose source is connected to the shift delay module, and whose drain is connected to the output terminal of the jth stage of shift register unit; and
the pull down unit comprises a second switch transistor whose gate is connected to the output terminal of the nth stage of virtual shift register unit, whose source is connected to the reference voltage terminal, and whose drain is connected to the gate of a gate line driving signal output transistor in the first stage of virtual shift register unit.

### Claim 14 (depends on 11)

The display apparatus of claim 11, wherein the repeat output module comprises an output unit and a pull down unit;
the shift delay module comprises i virtual shift register units connected in series, wherein the input terminal of the first stage of virtual shift register unit is connected to the output terminal of the jth stage of shift register unit, the output terminal of the ith stage of virtual shift register unit is connected to the pull down unit and the input terminal of the (j+1)th stage of shift register unit, and the clock control terminal is connected to the output unit, where i=2;
the output unit is configured to output the repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit under the control of the clock control terminal, where n=1; and
the pull down unit is also connected to the reference voltage terminal and an output control terminal of the first stage of virtual shift register unit, and is configured to control the first stage of virtual shift register unit by the voltage of the reference voltage terminal to output a signal to the next stage of virtual shift register unit, so as to control the output terminal of the ith stage of virtual shift register unit to stop outputting the repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit through the output unit.

### Claim 15 (depends on 13)

The display apparatus of claim 13, wherein the output unit comprises a first switch transistor whose gate is connected to the clock control terminal, whose source is connected to the shift delay module, and whose drain is connected to the output terminal of the jth stage of shift register unit; and
the pull down unit comprises a second switch transistor whose gate is connected to the output terminal of the nth stage of virtual shift register unit, whose source is connected to the reference voltage terminal, and whose drain is connected to the gate of a gate line driving signal output transistor in the first stage of virtual shift register unit.

### Claim 16 (depends on 10)

The display apparatus of claim 10, wherein
the repeat output module is also connected to a reference voltage terminal and the output terminal of the (j+1)th stage of shift register unit, and is configured to control the repeat output module by the voltage of the reference voltage terminal to stop outputting the repeat scan signal to the output terminal of the jth stage of shift register unit when the (j+1)th stage of shift register unit outputs the scan signal.

### Claim 17 (depends on 16)

The display apparatus of claim 16, wherein the repeat output module comprises an output unit and a pull down unit;
the shift delay module comprises one first stage of virtual shift register unit, wherein the input terminal of the first stage of virtual shift register unit is connected to the output terminal of the jth stage of shift register unit, the output terminal of the first stage of virtual shift register unit is connected to the input terminal of the (j+1)th stage of shift register unit, and the output unit is connected to the clock control terminal;
the output unit is configured to output the repeat scan signal to the output terminal of the jth stage of shift register unit under the control of the clock control terminal; and
the pull down unit is also connected to the reference voltage terminal, the output terminal of the (j+1)th stage of shift register unit and an output control terminal of the first stage of virtual shift register unit, and is configured to control the first stage of virtual shift register unit by the voltage of the reference voltage terminal to stop outputting the repeat scan signal to the output terminal of the jth stage of shift register unit when the (j+1)th stage of shift register unit outputs the scan signal.

### Claim 18

A gate line driving method for a gate driving circuit in which a shift delay module is arranged between the jth stage of shift register unit and the (j+1)th stage of shift register unit which are adjacent to each other, wherein j is a positive integer, comprising:
controlling a repeat output module to turn on by a clock control terminal after a touch time ends, such that the shift delay module outputs a repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit corresponding thereto previously through the repeat output module, wherein n is a positive integer and n is equal to or less than j; and
re-outputting a scan signal to a gate line by each of the shift register units from the (j−n+1)th stage to the jth stage in sequence.

### Claim 19 (depends on 18)

The method of claim 18, wherein stopping by the repeat output module the output of the repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit after re-outputting the scan signal by the jth stage of shift register unit.

### Claim 20 (depends on 18)

The method of claim 18, wherein stopping by the repeat output module the output of the repeat scan signal to the output terminal of the (j−n+1)th stage of shift register unit after the (j+1)th stage of shift register unit outputs the scan signal.