# US 9,519,330 B2 · Energy-efficient multicore processor architecture for parallel processing

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- Number: US 9,519,330 B2
- Document ID: US9519330B2
- Status: Granted
- Kind: B2
- Application number: 14/060,037
- Filed: 2013-10-22
- Published: 2015-04-23
- Granted: 2016-12-13
- Earliest claimed: 2013-10-22
- Assignees: Wisconsin Alumni Research Foundation
- Applicants: Wisconsin Alumni Research Foundation
- Inventors: Nam-Sung Kim
- Web page: https://patentgrep.com/patent/US9519330B2

## CPC

- G06F 1/324: by lowering clock frequency
- G06F 1/3296: by lowering the supply or operating voltage
- G06F 1/3228: Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
- G06F 1/3243: {Power saving in microcontroller unit}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A multicore computer architecture provides for clock dividers on each core, the clock dividers capable of providing rapid changes in the clock frequency of the core. The clock dividers are used to reduce the clock frequency of individual cores spinning while waiting for a synchronization instruction resolution such as a lock variable. Core power demands may be decreased before and after change in dock speed to reduce power bus disruption.

## Claims

### Claim 1

A computer system comprising:
multiple processor cores each having a processor core clock input and operating according to a clock signal received at the processor core clock input to execute instructions of an instruction set in synchrony with the clock signal; and
a frequency selector associated with each given processor core having a selector input for receiving at least two non-zero frequency stable clock signals, a selection input for receiving a desired frequency selection from the given processor core, and a selector output for outputting one of the frequency stable clock signals to the processor clock input depending on the selection input;
wherein the instruction set includes at least one instruction executing to change the selection input of a frequency selector associated with a processor core executing the at least one instruction;
wherein the at least two frequency stable clock signals are received from at least one state machine divider without feedback stability requirements;
wherein the at least one instruction of the instruction set is a synchronization instruction causing the frequency selector to select a reduced non-zero frequency-stable clock signal during a synchronization and causing the processor to spin while it waits for the synchronization to complete, to exit from the spin based on a event indicating synchronization is complete, and upon that exit causing the frequency selector to select an increased non-zero frequency-stable clock signal.

### Claim 2 (depends on 1)

The computer system of claim 1 wherein the frequency selector provides for selection among frequencies limited to frequencies related according to two to a power of an integer.

### Claim 3 (depends on 1)

The computer system of claim 1 wherein the at least one instruction changes the output clock between a first frequency substantially equal to the minimum operating frequency of the processor core and a second frequency higher than the first frequency.

### Claim 4 (depends on 3)

The computer system of claim 3 wherein the second value is substantially equal to a highest operating frequency among the processor cores.

### Claim 5 (depends on 3)

The computer system of claim 3 wherein the first frequency is at least 1/2 of the second frequency.

### Claim 6 (depends on 1)

The computer system of claim 1 wherein the frequency selector provides a change of output frequency from a first to a second frequency where the second frequency is stabilized within 10 μof the change.

### Claim 7 (depends on 1)

The computer system of claim 1 wherein the frequency selector is a programmable frequency divider associated with each given processor and receiving as a selector input a divisor wherein the output clock has a frequency lower than the input clock according to the divisor input.

### Claim 8 (depends on 7)

The computer system of claim 7 wherein the programmable frequency divider provides a binary counter whose output may be selected according to the divisor input.

### Claim 9 (depends on 7)

The computer system of claim 7 further including a clock signal providing a common clock signal and a phase locked loop associated with each given processor core, each phase locked loop receiving the common clock signal and providing an input clock signal to an associated programmable frequency divider of a given processor core.

### Claim 10 (depends on 1)

The computer system of claim 1 wherein at least one instruction of the instruction set is a synchronization instruction t providing an atomically executable memory access to read a lock variable.

### Claim 11 (depends on 1)

The computer system of claim 1 wherein the multiple processors are on a single integrated circuit.

### Claim 12

A computer system comprising:
multiple processor core each having a processor core clock input and operating according to a clock signal received at the processor core clock input to execute instructions of an instruction set in synchrony with the clock signal; and
a frequency selector associated with each given processor core haying a selector input for receiving at least two frequency stable clock signals, a selection input for receiving a desired frequency selection from the given processor core, and a selector output for outputting one of the frequency stable clock signals to the processor clock input depending on the selection input;
wherein the instruction set includes at least one instruction executing to change the selection input of a frequency selector associated with a processor core executing the at least one instruction:
wherein the at least two frequency stable clock signals are received from at least one state machine divider without feedback stability requirements;
wherein the at least one instruction provides a reduction in a processor core's execution capabilities that decreases core power consumption at a time before a change in selection input that decreases a frequency of the output clock to the processor core; the time before a change having a predetermined length to reduce electrical noise on a power distribution bus of the multiple processor cores.

### Claim 13 (depends on 12)

The computer system of claim 12 wherein the reduction in processor core's execution capabilities is an elimination of instruction fetch capabilities for fetching instructions of the instruction set from an electronic memory.

### Claim 14 (depends on 12)

The computer system of claim 12 wherein the at least one instruction provides a an increase in processor core's execution capabilities that increases power consumption at a time after a change in selection input that increases the frequency of the output clock to the processor, the time after a change having a predetermined length to reduce electrical noise on a power distribution bus of the multiple processor cores.

### Claim 15 (depends on 14)

The computer system of claim 14 wherein the increase in processor core's execution capabilities is a reestablishment of instruction fetch capabilities for fetching instructions of the instruction set from an electronic memory.

### Claim 16

A method of synchronizing multiple processor cores in a computer system having multiple processor cores each having a processor core clock input and operating according to a clock signal received at the processor core clock input to execute instructions of an instruction set in synchrony with the clock signal: and
a frequency selector associated with each given processor core having a selector input for receiving at least two frequency stable clock signals, a selection input for receiving a desired frequency selection from the given processor core, and a selector output for outputting one of the frequency stable clock signals to the processor clock input depending on the selection input;
wherein the instruction set includes at least one instruction executing to change the selection input of a frequency selector associated with a processor core's executing the at least one instruction;
wherein the at least one instruction of the instruction set is a synchronization instruction causing the frequency selector to select a reduced non-zero frequency-stable clock signal during a synchronization and causing the processor to spin while it waits for the synchronization to complete, to exit from the spin based on a event indicating synchronization is complete, and upon that exit causing frequency selector to select an increased non-zero frequency-stable clock signal;
the method comprising the steps of:
(a) providing execution of a program among the multiple processor cores, the program having synchronization points;
(b) in a given processor core, spinning at the synchronization points for a period of time in a synchronization process;
(c) at a beginning of the period of time, decreasing the output clock to the given processor core; and
(d) at an end of the period of time, increasing the output clock of the given processor core.

### Claim 17 (depends on 16)

The method of claim 16 wherein the synchronization process is selected from the group consisting of a lock acquisition, a conditional synchronization, and an arrival at a synchronization bather.

### Claim 18 (depends on 16)

The method of claim 16 wherein step (c) further includes the step of decreasing the functions of the given processor core before decreasing the output clock of the given processor core, and step (d) includes the step of increasing the functions of a given processor core before increasing the output clock of the given processor core.

### Claim 19 (depends on 1)

The computer system of claim 1 wherein the at least two frequency stable clock signals are generated by at least one divider after a single phase locked loop.