# US 9,519,325 B2 · Application processors, mobile devices including the same and methods of managing power of application processors

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- Number: US 9,519,325 B2
- Document ID: US9519325B2
- Status: Granted
- Kind: B2
- Application number: 14/283,948
- Filed: 2014-05-21
- Published: 2015-01-29
- Granted: 2016-12-13
- Earliest claimed: 2013-07-24
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Yong-Ki Byun; Dong-Han Lee; Jae-Sop Kong
- Inventors: Yong-Ki Byun; Dong-Han Lee; Jae-Sop Kong
- Web page: https://patentgrep.com/patent/US9519325B2

## CPC

- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F 1/325: {Power saving in peripheral device}
- G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)}
- G09G 5/36: characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G 5/39: Control of the bit-mapped memory
- G09G 2320/103: Detection of image changes, e.g. determination of an index representative of the image change
- G09G 2330/021: Power management, e.g. power saving
- G09G 2360/18: Use of a frame buffer in a display terminal, inclusive of the display panel
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

An application processor includes a memory controller, a display block and a power management unit. The memory controller controls an external memory that stores an image signal to be displayed on a display unit. The display block includes an internal frame buffer and a display controller and the display controller controls the image signal to be displayed on the display unit. The power management unit adaptively controls a power mode of the application processor based on a characteristic of the image signal to be displayed and a power control overhead index.

## Claims

### Claim 1

An application processor, comprising:
a memory controller configured to control a memory that stores an image data; and
a power management unit coupled to the memory controller;
wherein the power management unit is configured to control a power mode of the application processor based on a characteristic of the image data, based on a comparison of memory resources of an internal frame buffer and a memory request amount of the image data, and based on a power control overhead index, wherein the power control overhead index represents a time required for the application processor to transition from a first power mode to a second power mode and wherein the internal frame buffer is included in the application processor.

### Claim 2 (depends on 1)

The application processor of claim 1, further comprising an image processing block configured to process the image data for display on a display unit;
wherein the power management unit is farther configured to control a power mode of the image processing block based on the characteristic of the image data and the power control overhead index.

### Claim 3 (depends on 2)

The application processor of claim 2, wherein the power management unit is further configured to place the memory controller and the image processing block into a first low power mode or a second low power mode in response to determining that the image data represents a still image.

### Claim 4 (depends on 3)

The application processor of claim 3, wherein the application processor comprises a display control block including a display controller and the internal frame buffer, wherein in the first low power mode, the display control block routes the image signal data to the display unit through the internal frame buffer, and wherein in the second low power mode, the display control block routes the image signal data directly to the display unit bypassing the internal frame buffer.

### Claim 5 (depends on 2)

The application processor of claim 2, wherein the memory controller is coupled to a first power bus by a first transistor and the image processing block is coupled to a second power bus by a second transistor, and wherein the power management unit is configured to switch the first transistor and/or the second transistor based on the selected power mode of the image processing block and the memory controller.

### Claim 6 (depends on 2)

The application processor of claim 2, wherein the memory controller belongs to a first power domain and the image processing block belongs to a second power domain that is different from the first power domain.

### Claim 7 (depends on 2)

The application processor of claim 2, wherein the image data comprises a still image and wherein the power management unit is configured to control a power mode of the memory controller and the image processing block to be one of a plurality of low power modes having respective different power depths.

### Claim 8 (depends on 7)

The application processor of claim 7, wherein the plurality of low power modes include a first low power mode and a second low power mode, wherein the first low power mode has a plurality of sub low power modes having respective different power depths with respect to each other, and wherein the power management unit is configured to control the power mode of the memory controller and the image processing block to be one of the second low power mode and the plurality of sub low power modes based on the characteristic of the image data and a power control overhead index.

### Claim 9 (depends on 2)

The application processor of claim 2, wherein the power management unit is configured to return the power mode of the memory controller and the image processing block to a normal mode when the image data is to be updated.

### Claim 10

A mobile device, comprising:
a display unit configured to display an image data;
a memory configured to store the image data; and
an application processor configured to transmit the image data to the display unit;
wherein the application processor comprises:
a memory controller configured to control the memory; and
a power management unit coupled to the memory controller;
wherein the power management unit is configured to control a power mode of the application processor based on a characteristic of the image data, based on a comparison of memory resources of an internal frame buffer and a memory request mount of the image data and based on a power control overhead index wherein the waver control overhead index represents a time required for the application processor to transition from a first power mode to a second power mode and wherein the internal frame buffer is included in the application processor.

### Claim 11 (depends on 10)

The mobile device of claim 10, further comprising an image processing block configured to process the image data for display on a display unit;
wherein the power management unit is configured to control a power mode of the image processing block based on the characteristic of the image data and the power control overhead index.

### Claim 12

A method of operating an application processor including a memory controller that controls a memory that stores an image data, the method comprising:
determining a characteristic of the image data;
determining a power control overhead index wherein the power control overhead index represents a time required for the application processor to transition from a first power mode to second power mode; and
controlling a power mode of the application processor in response to the characteristic of the image data based on a comparison of memory resources of an internal frame buffer and a memory request amount of the image data and based on the power control overhead index, wherein the internal frame buffer is included in the processor.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
controlling a power mode of an image processing block based on the characteristic of the image data and the power control overhead index.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
placing the memory controller and the image processing block into a first low power mode or a second low power mode in response to determining that the image data represents a still image.

### Claim 15 (depends on 14)

The method of claim 14, further comprising routing the image data to a display unit through an internal frame buffer when the memory controller and the image processing block are in the first low power mode, and routing the image data directly to the display unit bypassing the internal frame buffer when the memory controller and the image processing block are in the second low power mode.

### Claim 16 (depends on 13)

The method of claim 13, wherein the memory controller is coupled to a first power bus by a first transistor and the image processing block is coupled to a second power bus by a second transistor, wherein the method further comprises:
switching the first transistor and/or the second transistor based on the selected power mode of the image processing block and the memory controller.

### Claim 17 (depends on 13)

The method of claim 13, wherein the image data comprises a still image and wherein the method further comprises controlling a power mode of the memory controller and the image processing block to be one of a plurality of low power modes having respective different power depths.

### Claim 18 (depends on 17)

The method of claim 17, wherein the plurality of low power modes include a first low power mode and a second low power mode, wherein the first low power mode has a plurality of sub low power modes having respective different power depths with respect to each other, and wherein the method further comprises controlling the power mode of the memory controller and the image processing block to be one of the second low power mode and the plurality of sub low power modes based on the characteristic of the image data and a power control overhead index.