# US 9,519,324 B2 · Local power gate (LPG) interfaces for power-aware operations

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- Number: US 9,519,324 B2
- Document ID: US9519324B2
- Status: Granted
- Kind: B2
- Application number: 14/225,612
- Filed: 2014-03-26
- Published: 2015-10-01
- Granted: 2016-12-13
- Earliest claimed: 2014-03-26
- Assignees: Intel Corporation
- Applicants: Michael Mishaeli; Ron Gabor; Robert C. Valentine; Alex Gerber; Zeev Sperber
- Inventors: Michael Mishaeli; Ron Gabor; Robert C. Valentine; Alex Gerber; Zeev Sperber
- Web page: https://patentgrep.com/patent/US9519324B2

## CPC

- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 9/22: Microcontrol or microprogram arrangements
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Technologies for local power gate (LPG) interfaces for power-aware operations are described. A processor includes locally-gated circuitry of a core, main core circuitry of the core, the main core, and local power gate (LPG) hardware. The LPG hardware is to power gate the locally-gated circuitry according to local power states of the LPG hardware. The main core decodes a first instruction of a set of instructions to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The main core monitors a current local power state of the LPG hardware, selects one of the code paths based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the locally-gated circuitry and continues execution of the first power-aware operation without waiting for the locally-gated circuitry to be powered up.

## Claims

### Claim 1

A processor comprising:
locally-gated circuitry of a core;
main core circuitry of the core, the main core comprising a decode unit and an execution unit; and
local power gate (LPG) hardware coupled to the locally-gated circuitry and the main core circuitry, the LPG hardware to power gate the locally-gated circuitry according to local power states of the LPG hardware,
wherein the decode unit is to decode a first instruction of a set of instructions to perform a first power-aware operation of a specified length, the first instruction to compute an execution code path for execution, and
wherein the execution unit is to:
execute a first micro-operation to monitor a current local power state of the LPG hardware;
execute a second micro-operation to select one of a plurality of code paths based on the current local power state, the specified length, and a specified threshold; and
execute a third micro-operation in the selected one of the plurality of code paths to issue a hint to the LPG hardware to power up the locally-gated circuitry and to continue execution of the first power-aware operation without waiting for the locally-gated circuitry to be powered up.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the second micro-operation is operative to:
program a jump-table register to point to a first-length code path of the plurality of code paths when the current local power state allows execution of micro-operations of the first length and the specified length is shorter than the specified threshold;
program the jump-table register to point to a second-length code path of the plurality of code paths when the current local power state allows execution of the micro-operations of the second length and the specified length is shorter than the specified threshold, the second length being greater than the first length; and
program the jump-table register to point to a third-length code path of the plurality of code paths when the specified length is longer than the specified threshold, the third length being greater than the second length, wherein the first micro-operation is further operative to map a power level indication of the current lower power state to a first mode-based-branch micro-operation that allows execution in the first-length code path until the locally-gated circuitry is powered up and then continue the execution in the third-length code path.

### Claim 3 (depends on 2)

The processor of claim 2, wherein, when the first-length code path is selected, the execution unit is further operative to:
execute the third micro-operation at a beginning of the first-length code path to initiate a power-up sequence by the LPG hardware to power up the locally-gated circuitry to execute a second set of subsequent micro-operations of the second length in the second-length code path; and
without waiting for the power-up sequence to complete, execute a first set of subsequent micro-operations of the first length in the second-length code path.

### Claim 4 (depends on 3)

The processor of claim 3, wherein the execution unit is further operative to execute the second set of subsequent micro-operations of the second length in the second-length code path when the power-up sequence is completed.

### Claim 5 (depends on 2)

The processor of claim 2, wherein, when the second-length code path is selected, the execution unit is further operative to execute subsequent micro-operations of the second length in the second-length code path.

### Claim 6 (depends on 2)

The processor of claim 2, wherein, when the third-length code path is selected, the execution unit is further operative to:
execute the third micro-operation at a beginning of the third-length code path to initiate a power-up sequence by the LPG hardware to power up the locally-gated circuitry to execute a second set of subsequent micro-operations of the third length in the third-length code path; and
without waiting for the power-up sequence to complete, execute a first set of subsequent micro-operations of the first length in the third-length code path.

### Claim 7 (depends on 6)

The processor of claim 6, wherein the execution unit is further to execute the second set of subsequent micro-operations of the third length in the third-length code path when the power-up sequence is completed.

### Claim 8 (depends on 2)

The processor of claim 2, wherein, when the third-length code path is selected, the execution unit is further to:
execute the third micro-operation at a beginning of the third-length code path to initiate a power-up sequence by the LPG hardware to power up the locally-gated circuitry to execute a second set of subsequent micro-operations of the third length in the third-length code path;
execute a fourth micro-operation to check for an insufficient current supply license in which a micro-operation scheduler throttles execution by dispatching the micro-operations at a specified clock cycle instead of every clock cycle, wherein the first micro-operation is further to map a current-supply license indication to a second mode-based-branch micro-operation that allows execution of the first power-aware operation in the second-length code path when there is insufficient current supply license and allows execution of the first power-aware operation in the third-length code path when there is sufficient current supply license;
when there is insufficient current supply license, execute a first set of subsequent micro-operations of the second length in the second-length code path; and
execute the second set of subsequent micro-operations of the third length in the third-length code path when the power-up sequence is completed.

### Claim 9 (depends on 1)

The processor of claim 1, wherein the first power-aware operation is a repeat (REP) string operation, wherein the first-length code path is a 16-byte code path, the second-length code path is a 32-byte code path, and the third-length code path is a 64-byte code path.

### Claim 10 (depends on 1)

The processor of claim 1, wherein the decode unit is to decode a second instruction of the set of instructions to compute an early tail condition, wherein the execution unit is further to:
execute a sixth micro-operation to compute the early tail condition based on the second instruction; and
execute the second micro-operation to select one of the plurality of code paths when there is no early tail in view of the early tail condition; and
not execute the second micro-operation when there is an early tail in the view of the early tail condition.

### Claim 11

A processor comprising:
a microcode store of a core, the microcode store to store microcode;
local power gate (LPG) hardware coupled to locally-gated circuitry of the core; and
main core circuitry of the core, wherein the core is to execute the microcode to:
monitor a current status of the locally-gated circuitry;
select a first code path of a plurality of code paths for execution when the current status allows execution of micro-operations of a first length only and a current string operation is shorter in length than a pre-defined threshold;
select a second code path of the plurality of code paths for execution when the current status allows execution of the micro-operations of a second length only and the current string operation is shorter in length than the pre-defined threshold;
select a third code path of the plurality of code paths for execution of the micro-operations of a third length when the current string operation is longer in length than the pre-defined threshold;
at a beginning of the first code path, initiate a first power-up sequence by the LPG hardware to power up the locally-gated circuitry for execution of the micro-operations of the second length and continue execution of the micro-operations of the first length without waiting for the first power-up sequence to complete; and
at a beginning of the third code path, initiate a second power-up sequence by the LPG hardware to power up the locally-gated circuitry for execution of the micro-operations of the third length and continue execution of the micro-operations of at least the first length or the second length without waiting for the second power-up sequence to complete.

### Claim 12 (depends on 11)

The processor of claim 11, wherein the microcode is further operative to:
check a throttling status of a micro-operation scheduler at the beginning of the third code path;
when the micro-operation scheduler is throttling, continue execution of the micro-operations of the second length; and
when the micro-operation scheduler is not throttling, continue execution of the micro-operations of the third length.

### Claim 13 (depends on 11)

The processor of claim 11, wherein the microcode is further operative to:
program a jump-table register to point to the first code path with a first execution loop of the first length when the first code path is selected;
program the jump-table register to point to the second code path with a second execution loop of the second length when the second code path is selected; and
program the jump-table register to point to the third code path with a third execution loop of the third length when the third code path is selected.

### Claim 14 (depends on 11)

The processor of claim 11, wherein the microcode is further operative to map a power level indication of the LPG hardware to a first zero-penalty, mode-based-branch micro-operation that allows execution of the current string operation using the micro-operations of the first length in the first code path until the second power-up sequence completes and then continue the execution of the current string operation using the micro-operations of the third length in the third code path.

### Claim 15 (depends on 14)

The processor of claim 14, wherein the microcode is further operative to map a current-supply license indication to a second zero-penalty, mode-based-branch micro-operation that allows execution of the current string operation using the micro-operations of the second length in the second code path.

### Claim 16

A method comprising:
monitoring, by microcode executed by a processor, a current status of a locally-gated circuitry of a core of the processor, wherein the locally-gated circuitry is power gated by local power gate (LPG) hardware;
selecting a first code path of a plurality of code paths for execution when the current status allows execution of micro-operations of a first length only and a current string operation is shorter in length than a pre-defined threshold;
selecting a second code path of the plurality of code paths for execution when the current status allows execution of the micro-operations of a second length only and the current string operation is shorter in length than the pre-defined threshold;
selecting a third code path of the plurality of code paths for execution of the micro-operations of a third length when the current string operation is longer in length than the pre-defined threshold;
at a beginning of the first code path,
initiating a first power-up sequence by the LPG hardware to power up the locally-gated circuitry for execution of the micro-operations of the second length, and
continuing execution of the micro-operations of the first length without waiting for the first power-up sequence to complete; and
at a beginning of the third code path,
initiating a second power-up sequence by the LPG hardware to power up the locally-gated circuitry for execution of the micro-operations of the third length, and
continuing execution of the micro-operations of at least the first length or the second length without waiting for the second power-up sequence to complete.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
checking a throttling status of a micro-operation scheduler at the beginning of the third code path;
when the micro-operation scheduler is throttling, continuing execution of the micro-operations of the second length; and
when the micro-operation scheduler is not throttling, continuing execution of the micro-operations of the third length.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
programing a jump-table register to point to the first code path with a first execution loop of the first length when the first code path is selected;
programing the jump-table register to point to the second code path with a second execution loop of the second length when the second code path is selected; and
programing the jump-table register to point to the third code path with a third execution loop of the third length when the third code path is selected.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
mapping a power level indication of the LPG hardware to a first zero-penalty, mode-based-branch micro-operation that allows execution of a first power-aware operation using the micro-operations of the first length in the first code path until the second power-up sequence completes; and
continuing the execution of the current string operation using the micro-operations of the third length in the third code path.

### Claim 20 (depends on 19)

The method of claim 19, further comprising mapping a current-supply license indication to a second zero-penalty, mode-based-branch micro-operation that allows execution of the current string operation using the micro-operations of the second length in the second code path.