# US 9,519,302 B2 · Semiconductor apparatus including multichip package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,519,302 B2 - Document ID: US9519302B2 - Status: Granted - Kind: B2 - Application number: 14/664,524 - Filed: 2015-03-20 - Published: 2016-06-09 - Granted: 2016-12-13 - Earliest claimed: 2014-12-05 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Chang Hyun Kim; Choung Ki Song - Web page: https://patentgrep.com/patent/US9519302B2 ## CPC - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G05F 3/02: Regulating voltage or current - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 7/1066: {Output synchronization} - G11C 7/1093: {Input synchronization} - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 90/00: Package configurations - G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} - H10W 72/07254: {changes in dispositions} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/247: {Dispositions of multiple bumps} - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - G11C: STATIC STORES (semiconductor memory devices H10B) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor apparatus including a multichip package is disclosed. The semiconductor apparatus includes a slave chip having a slave region and a master region. The slave region is configured to have a first threshold voltage smaller than an operation voltage and the master region is configured to have a second threshold voltage greater than the operation voltage. ## Claims ### Claim 1 A semiconductor apparatus comprising: a master chip including a first master region and a first slave region; a slave chip stacked on the master chip and including a second master region and a second slave region; and a voltage providing unit configured to set the first master region, the first slave region, and the second slave region to a first threshold voltage smaller than an operation voltage and set the second master region to a second threshold voltage greater than the operation voltage, wherein the voltage providing unit is configured to provide an operation bulk voltage to the first master region, the first slave region, and the second slave region, and a standby bulk voltage smaller than the operation bulk voltage to the second master region. ### Claim 2 (depends on 1) The semiconductor apparatus of claim 1, wherein the voltage providing unit is located in one selected from the master chip and the slave chip. ### Claim 3 (depends on 1) The semiconductor apparatus of claim 1, wherein the voltage providing unit includes: a first bulk voltage generator configured to generate the operation bulk voltage; a second bulk voltage generator configured to generate the standby bulk voltage; a setting circuit unit configured to set an output condition of the standby bulk voltage; and a selection unit configured to receive the operation bulk voltage and the standby bulk voltage, and selectively output the operation bulk voltage and the standby bulk voltage as a first internal voltage and a second internal voltage. ### Claim 4 (depends on 3) The semiconductor apparatus of claim 3, wherein the setting circuit unit is configured to set the output condition according to a slave chip determination signal to determine whether a semiconductor chip to which the first and second internal voltages are output is the master chip or the slave chip, and a stacking determination signal to determine whether or not the semiconductor apparatus is a multichip package in which at least two semiconductor chips are stacked. ### Claim 5 (depends on 4) The semiconductor apparatus of claim 4, wherein the slave chip determination signal and the stacking determination signal are set in a control block of the master chip. ### Claim 6 (depends on 4) The semiconductor apparatus of claim 4, wherein the selection unit is configured to output the operation bulk voltage as the first and second internal voltages when the semiconductor apparatus is a multichip package, and the first and second internal voltages are provided to the master chip. ### Claim 7 (depends on 6) The semiconductor apparatus of claim 6, wherein the selection unit is configured to output the operation bulk voltage as the first internal voltage and the standby bulk voltage as the second internal voltage when the semiconductor apparatus is a multichip package and the first and second internal voltages are provided to the slave chip, and the first internal voltage is provided to the second slave region of the slave chip, and the second internal voltage is provided to the second master region of the slave chip. ### Claim 8 (depends on 3) The semiconductor apparatus of claim 3, wherein the operation bulk voltage is a ground voltage (VSS) and the standby bulk voltage is a negative voltage (VBB). ### Claim 9 A semiconductor apparatus comprising: a slave chip having a slave region and a master region, wherein the slave region is configured to have a first threshold voltage smaller than an operation voltage and the master region is configured to have a second threshold voltage greater than the operation voltage, wherein the slave chip includes a voltage providing unit, and the voltage providing unit is configured to provide an operation bulk voltage to the slave region, and provide a standby bulk voltage having a smaller level than the operation bulk voltage to the master region.