# US 9,519,041 B2 · System and method for providing an accurate and cost-effective current sensor calibration

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- Number: US 9,519,041 B2
- Document ID: US9519041B2
- Status: Granted
- Kind: B2
- Application number: 14/465,767
- Filed: 2014-08-21
- Published: 2016-02-25
- Granted: 2016-12-13
- Earliest claimed: 2014-08-21
- Assignees: QUALCOMM Incorporated
- Applicants: Qualcomm Incorporated
- Inventors: Mahadevamurty Nemani
- Web page: https://patentgrep.com/patent/US9519041B2

## CPC

- G01R 35/005: {Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references (G01R33/0035, G01R35/002 take precedence)}
- G01K 13/00: Thermometers specially adapted for specific purposes
- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G01K: MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR (radiation pyrometry G01J5/00)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems and methods for calibrating on-die analog current sensors are disclosed. The methods can be routinely applied to perform a calibration such as during a system initialization or boot procedure or during other times when the system is in a sleep or power saving mode of operation. The systems determine a leakage current in the device under present environmental conditions. A baseline load current determined under the present temperature and input voltage is retrieved and used to determine a total leakage current. A reproducible and stable dynamic load is controllably applied to provide a known current to the on-die analog current sensor. A third mechanism permits repeatable adjustments to the known current that span the operational range of the on-die integrated current sensor. The responsiveness of the disclosed mechanisms ensures that temperature induced leakage does not increase significantly during a current sensor calibration.

## Claims

### Claim 1

A method for calibrating an integrated analog current sensor in a computing device, the method comprising:
applying power to an application processing system without enabling a clock network;
recording a measure of a leakage current of a processing resource;
recording at least one measured parameter for the processing resource;
retrieving a baseline leakage current for the processing resource responsive to the at least one measured parameter;
enabling the clock network, where the clock network is responsive to a first input signal and a second input signal to generate a dynamic load;
measuring a load current with the integrated analog current sensor being calibrated;
generating an estimate of the load current responsive to capacitance of the clock network, a clock frequency and an input voltage;
calculating a total current applied responsive to the leakage current and the estimate of the load current;
recording the total current applied and the load current;
adjusting the second input signal to adjust the dynamic load; and
repeating the measuring, generating, recording the total current applied and the load current, and adjusting steps a desired number of times.

### Claim 2 (depends on 1)

The method of claim 1, wherein the at least one measured parameter is selected from the group consisting of temperature and supply voltage.

### Claim 3 (depends on 2)

The method of claim 2, wherein the temperature is measured with a temperature sensor integrated in one of the application processing system and a graphics processing unit.

### Claim 4 (depends on 1)

The method of claim 1, wherein the at least one measured parameter is recorded with the clock network disabled.

### Claim 5 (depends on 1)

The method of claim 1, wherein the at least one measured parameter is recorded with the application processing system in a reset mode of operation.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first input signal is applied to an input of a phase-locked loop.

### Claim 7 (depends on 1)

The method of claim 1, wherein the second input signal is applied to gating elements in the clock network.

### Claim 8 (depends on 1)

The method of claim 1, wherein using the clock network includes waiting until a phase-locked loop lock condition is achieved before enabling clock logic in the clock network.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
before the recording the at least one measured parameter,
verifying that the application processing system is in a power-on condition; and
when the application processing system is not in the power-on condition,
applying power to the application processing system.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
before the recording the at least one measured parameter,
verifying that the clock network is in a disabled condition; and
when the clock network is not in the disabled condition,
disabling the clock network.

### Claim 11 (depends on 1)

The method of claim 1, wherein the leakage current is a component of a first data point for a calibration.

### Claim 12 (depends on 11)

The method of claim 11, wherein each instance of the total current applied identifies a component of a corresponding subsequent data point for the calibration.

### Claim 13 (depends on 12)

The method of claim 12, wherein the calibration defines a piece-wise linear trace over a range of the integrated analog current sensor.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
performing a reset procedure.

### Claim 15

A computing device, comprising:
means for applying power to an application processing system without enabling a clock network configured to provide inputs to a processor of the application processing system;
means for measuring a leakage current while the clock inputs to the processor of the application processing system are disabled;
means for recording the leakage current of the processor;
means for retrieving a baseline current load as a result of operation of the processor at a present temperature and input voltage;
means for recording a total leakage current responsive to the leakage current and the baseline current load, the total leakage current corresponding to a first data point;
means for enabling the clock network to apply an adjustable dynamic load;
means for measuring a load current in an analog current sensor being calibrated, the means for measuring responsive to the adjustable dynamic load; and
means for determining an applied current as a function of the total leakage current and the load current, the applied current corresponding to a second data point.

### Claim 16 (depends on 15)

The computing device of claim 15, wherein the means for applying the adjustable dynamic load is responsive to a total capacitance of the clock network.

### Claim 17 (depends on 15)

The computing device of claim 15, wherein the means for applying, the means for measuring, and the means for determining are used to generate subsequent data points.

### Claim 18 (depends on 17)

The computing device of claim 17, further comprising:
means for generating a piece-wise linear trace responsive to the first data point, the second data point and subsequent data points.

### Claim 19 (depends on 15)

The computing device of claim 15, wherein the means for applying the adjustable dynamic load is responsive to a supply voltage and a clock frequency.