# US 9,519,025 B2 · Tap and aux circuitry with multiplexers on TDI, TDO, AUXI/O

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- Number: US 9,519,025 B2
- Document ID: US9519025B2
- Status: Granted
- Kind: B2
- Application number: 14/837,786
- Filed: 2015-08-27
- Published: 2015-12-24
- Granted: 2016-12-13
- Earliest claimed: 2004-06-17
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US9519025B2

## CPC

- G01R 31/318558: {Addressing or selecting of subparts of the device under test}
- G01R 31/2851: {Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318594: {Timing aspects (clock circuits G01R31/318552)}
- G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals}
- G01R 31/318572: {Input/Output interfaces}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

## Claims

### Claim 1

An integrated circuit comprising:
A. a serial instruction register having a serial data input coupled to a test data input, a serial data output, an instruction register control bus output, and a control bus input;
B. a serial data register having a serial data input coupled to the test data input, a serial data output, and a control input coupled to the instruction register control bus output;
C. first multiplexer circuitry coupling the serial data output of the instruction register and the serial data output of the data register to a test data output, and having a control input;
D. TAP control circuitry having a test clock input, a test mode select input, and a TAP control bus output coupled to the control bus input of the instruction register and the control input of the first multiplexer circuitry;
E. auxiliary circuitry coupled to the serial instruction register, the TAP control circuitry, the test data input, the test data output, and having a first control output, a first auxiliary input and a first auxiliary output;
F. second multiplexer circuitry having a first input coupled with the test data input, a second input, and an output coupled with the serial data input of the serial instruction register and the serial data register;
G. an input buffer having an input coupled to an auxiliary input and output lead and an output coupled with the first auxiliary input and the second input of the second multiplexer circuitry;
H. a tristate output buffer having an input coupled with the first auxiliary output, an output coupled with the auxiliary input and output lead, and a control input; and
I. third multiplexer circuitry having a first input coupled with the first control output, a second input having a fixed logic state, and an output coupled with the control input of the tristate output buffer.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 in which the auxiliary circuitry is one of a debug circuit, emulation circuit, in-circuit programming circuit, I/O communication circuit, triggering circuit, and breakpoint circuit.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 in which the auxiliary circuitry is a digital test circuit.

### Claim 4 (depends on 1)

The integrated circuit of claim 1 in which the auxiliary circuitry is an analog test circuit.