# US 9,519,020 B2 · Semiconductor apparatus and chip selecting method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,519,020 B2 - Document ID: US9519020B2 - Status: Granted - Kind: B2 - Application number: 13/760,242 - Filed: 2013-02-06 - Published: 2013-06-13 - Granted: 2016-12-13 - Earliest claimed: 2010-03-31 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jae Bum Ko; Jun Gi Choi - Web page: https://patentgrep.com/patent/US9519020B2 ## CPC - G01R 31/2607: {Circuits therefor (G01R31/2642 takes precedence)} - G06F 17/00: Digital computing or data processing equipment or methods, specially adapted for specific functions (information retrieval, database structures or file system structures therefor G06F16/00) - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 29/027: {in fuses} - G11C 29/785: {with redundancy programming schemes} - G11C 29/848: {by adjacent switching} - G11C 29/883: {using a single defective memory device with reduced capacity, e.g. half capacity} - H10W 72/01: {Manufacture or treatment} - H10W 90/00: Package configurations - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals. ## Claims ### Claim 1 A semiconductor apparatus comprising: an individual chip designating code setting circuit configured to generate a plurality of individual chip designating codes of different values in response to a plurality of start codes generated by shifting a start pulse in response to a clock; an individual chip activation circuit configured to receive the plurality of individual chip designating codes and an individual chip control code, enable one individual activation signal among a plurality of individual chip activation signals in response to the individual chip designating code and the individual chip control code; and a control circuit configured to receive a chip selection address, chip selection fuse signals, test fuse signals, and output the individual chip control code being set in response to the chip selection fuse signals and the test fuse signals or output the chip selection address as the individual chip control code in response to the chip selection fuse signals and the test fuse signals wherein the individual chip activation circuit performs an operation that matches the individual chip designating codes with the individual chip control code, and enables one individual activation signal according to a result of the operation. ### Claim 2 (depends on 1) The semiconductor apparatus according to claim 1, wherein the individual chip designating code setting circuit generates the individual chip designating code having the same number of bits. ### Claim 3 (depends on 1) The semiconductor apparatus according to claim 1, wherein the individual chip activation circuit comprises a plurality of comparison units that are configured to compare the individual chip designating code and the individual chip control code, and generate the individual chip activation signals. ### Claim 4 (depends on 1) The semiconductor apparatus according to claim 1, wherein the control circuit comprises: a selection code generation circuit configured to set a selection code or output the plurality of chip selection address as the selection code in response to the chip selection fuse signals; and a selective inversion output unit configured to invert a predetermined bit of the selection code in response to the test fuse signals, and generate the individual chip control code from at least the inverted bit of the selection code. ### Claim 5 (depends on 4) The semiconductor apparatus according to claim 4, wherein the chip selection fuse signals comprise first through third chip selection fuse signals and the selection code comprises 2 bits, and wherein the selection code generation circuit comprises: a first selection unit configured to fix all bits of the selection code to a specified level when the first chip selection fuse signal is enabled; a second selection unit configured to fix one predetermined bit of the selection code to the specified level and output one of the chip selection address as an unfixed bit of the selection code when the second chip selection fuse signal is enabled; and a third selection unit configured to output the chip selection address as the selection code when the third chip selection fuse signal is enabled. ### Claim 6 (depends on 5) The semiconductor apparatus according to claim 5, wherein the second selection unit fixes a most significant bit of the selection code to a specified level and outputs a least significant bit address of the chip selection address as a least significant bit of the selection code when the second chip selection fuse signal is enabled. ### Claim 7 (depends on 4) The semiconductor apparatus according to claim 4, wherein the selection code comprise 2 bits and the test fuse signals comprise first and second test fuse signals, and wherein the selective inversion output unit inverts or does not invert one bit of the selection code and outputs the inverted or non-inverted bit as one bit of the individual chip control code, in response to the first test fuse signal, and inverts or does not invert the other bit of the selection code and outputs the inverted or non-inverted bit as the other bit of the individual chip control code, in response to the second test fuse signal. ### Claim 8 (depends on 7) The semiconductor apparatus according to claim 7, wherein the selective inversion output unit comprises: a first inversion section configured to receive one bit of the selection code; a second inversion section configured to receive the other bit of the selection code; a first multiplexer configured to output one bit of the selection code or an output signal of the first inversion section as one bit of the individual chip control code, in response to the first test fuse signal; a second multiplexer configured to output the other bit of the selection code or an output signal of the second inversion section as the other bit of the individual chip control code, in response to the second test fuse signal. ### Claim 9 (depends on 1) The semiconductor apparatus according to claim 1, wherein the individual chip designating code setting circuit comprises: a shifting unit configured to receive the clock and the start pulse and generate the plurality of start codes of different values, an encoding unit configured to encode the plurality of start codes and generate a plurality of activation codes of different values, and a latch unit configured to latch the plurality of activation codes and output the plurality of individual chip designating codes.