Protection against side channels

A computer-readable non-transitory storage medium storing a set of instructions which, when executed by a processor of an electronic device, causes the processor to implement a protection method for protecting an electronic device, when the electronic device implements a cryptographic algorithm, against side channel attacks, the cryptographic algorithm working with a state array, the cryptographic algorithm being designed to generate, from a current state array, a second state array in which each row is obtained by shifting the corresponding row of the current state array, then to generate, from the second state array, a third state array in which the elements of each column are the result of mixing elements of the corresponding column of the second state array, the method comprising replacing said two consecutive generations of the respective second and third state array by a secure generation, from the current state array, of a state array equal to the third state array, this secure generation mixing, in a randomized order, the elements of the current state array that would have been located in a same column of the second state array if said second state array had been generated, in order to produce the corresponding column of the generated state array.

An electronic device (SCARD) arranged to implement a cryptographic algorithm (AES) working with a state array, the cryptographic algorithm (AES) being designed to generate (SHFT_R), from a current state array (MAT1), a second state array (MAT2) in which each row is obtained by shifting the corresponding row of the current state array (MAT1), then to generate (MIX_C), from the second state array (MAT2), a third state array (MAT3) in which the elements of each column are the result of mixing elements of the corresponding column of the second state array (MAT2), the electronic device (SCARD) comprising a protection circuit (MP) to protect against side channel attacks, the protection circuit (MP) being arranged to replace said two consecutive generations (SHFT_R, MIX_C) of the respective second and third state array (MAT2, MAT3) by a secure generation (SEC_GEN), from the current state array (MAT1), of a state array equal to the third state array (MAT3), this secure generation (SEC_GEN) mixing, in a randomized order, the elements of the current state array (MAT1) that would have been located in a same column of the second state array (MAT2) if said second state array had been generated, in order to produce the corresponding column of the generated state array.