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US 9,514,850 B2Granted
Memory device with improved refresh scheme for redundancy word line
AssigneeSK hynix Inc.
InventorSang-Hee Kim
Life of this patent
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Abstract
A memory device includes a plurality of redundancy word lines each of which is coupled with a plurality of redundancy memory cells, and a redundancy refresh circuit suitable for sequentially refreshing first redundancy word lines that are selected as target word lines for an additional refresh operation among the plurality of the redundancy word lines.
Claims20
A memory device, comprising:
- a plurality of redundancy word lines, each of which is coupled with a plurality of redundancy memory cells;
- and
- a redundancy refresh circuit suitable for sequentially refreshing first redundancy word lines that are selected as target word lines for an additional refresh operation among the plurality of the redundancy word lines,
- wherein the first redundancy word lines are selected as the target word lines based on the total number of second redundancy word lines that are used for a repair operation among the plurality of the redundancy word lines.
1 more element
A memory device, comprising:
- a plurality of normal word lines each of which is coupled with a plurality of normal memory cells;
- a plurality of redundancy word lines each of which is coupled with a plurality of redundancy memory cells;
- a normal refresh circuit suitable for sequentially refreshing unrepaired normal word lines among the plurality of the normal word lines and first redundancy word lines that are used for a repair operation among the plurality of the redundancy word lines, when a refresh signal is enabled;
- and
- a redundancy refresh circuit suitable for sequentially refreshing second redundancy word lines that are selected as target word lines for an additional refresh operation among the plurality of the redundancy word lines, when a redundancy refresh signal is enabled,
- wherein the redundancy refresh signal is enabled whenever the refresh signal is enabled a predetermined number of times.
3 more elements
A memory device, comprising:
- a plurality of redundancy word lines suitable for repairing a plurality of normal word lines;
- a normal refresh circuit suitable for sequentially refreshing first redundancy word lines that are used to repair the plurality of the normal word lines among the plurality of the redundancy word lines, for a refresh operation;
- and
- a redundancy refresh circuit suitable for sequentially refreshing second redundancy word lines that are selected as target word lines among the first redundancy word lines, for an additional refresh operation which is performed once when the refresh operation is performed a predetermined number of times.
1 more element
Dependencies are inferred from the claim text.