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US 9,514,803 B2Granted
Semiconductor memory having electrically floating body transistor
AssigneeZeno Semiconductor, Inc.
InventorsYuniarto Widjaja, Zvi Or-Bach
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Abstract
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
Claims20
A semiconductor memory cell comprising:
- a transistor comprising a source region, a floating body region, a drain region, and a gate;
- a first bipolar device having a first floating base region, a first emitter, and a first collector;
- and
- a second bipolar device having a second floating base region, a second emitter, and a second collector,
- wherein said first floating base region and said second floating base region are common to said floating body region;
- wherein said first collector is common to said second collector;
- wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell, and
- wherein said transistor is usable to access said memory cell.
5 more elements
A semiconductor memory array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
- a transistor comprising a source region, a floating body region, a drain region, and a gate;
- a first bipolar device having a first floating base region, a first emitter, and a first collector;
- and
- a second bipolar device having a second floating base region, a second emitter, and a second collector;
- wherein said first floating base region and said second floating base region are common to said floating body region;
- wherein said first collector is common to said second collector;
- and
- wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell, wherein said transistor is usable to access said memory cell;
- and
- wherein said first and second collectors are commonly connected to at least two of said memory cells.
8 more elements
An integrated circuit comprising:
- an array of semiconductor memory cells formed in a semiconductor substrate having at least one surface, the array comprising:
- said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
- a transistor comprising a source region, a floating body region, a drain region, and a gate;
- a first bipolar device having a first floating base region, a first emitter, and a first collector;
- and
- a second bipolar device having a second floating base region, a second emitter, and a second collector;
- a first control circuit configured to provide electrical signals to said first and second collectors, and
- a second control circuit configured to provide electrical signals to said transistor to access said memory cell;
- wherein said first floating base region and said second floating base region are common to said floating body region;
- wherein said first collector is common to said second collector;
- wherein at least one of said first bipolar device and said second bipolar device maintains a state of said memory cell;
- wherein said transistor is usable to access said memory cell;
- wherein said first and second collectors are commonly connected to at least two of said memory cell.
10 more elements
Dependencies are inferred from the claim text.