Receiving circuit with ultra-wide common-mode input voltage range

A receiving circuit with an ultra-wide common-mode input voltage range, which is electrically connected with an output end of a receiving circuit of a controller area network (CAN) and applicable to a transceiver integration circuit of said controller area network, comprising:

• a resistor assembly electrically connected with a high end and a low end of said controller area network (CANH and CANL) and including a first resistor, a second resistor, a third resistor and a fourth resistor, wherein a first node is arranged between said first resistor and said second resistor, and a second node is arranged between said third resistor and said fourth resistor, and wherein said first resistor is electrically connected with said high end and said first node, and said fourth resistor is electrically connected with said low end and said second node, and wherein said resistor assembly receives a high end voltage (VCANH) from said high end and a low end voltage (VCANL) from said low end and bucks voltage to generate and output a high end voltage division (VCANHDIV) at said first node and a low end voltage division (VCANLDIV) at said second node;
• a reference amplifier having a reference amplifier input end and a reference amplifier output end, wherein said reference amplifier input end is electrically connected with a reference voltage source, and said reference amplifier output end is electrically connected with a contact between said second resistor and said third resistor;
• a first input amplifier assembly and a second input amplifier assembly, wherein said first input amplifier assembly has a first input amplifier assembly output end, and said second input amplifier assembly has a second input amplifier output end, and wherein said first input amplifier assembly is electrically connected with a power source end, said first node and said second node, and wherein said second input amplifier assembly is electrically connected with a ground terminal, said first node and said second node, and wherein each of said first input amplifier assembly and said second input amplifier assembly receives said high end voltage division (VCANHDIV) from said first node and receives said low end voltage division (VCANLDIV) from said second node, and wherein said first input amplifier assembly outputs a first single-end output signal from said first input amplifier assembly output end, and wherein said second input amplifier assembly outputs a second single-end output signal from said second input amplifier assembly output end;
• and
• an analog adder having an analog adder input end and an analog adder output end, wherein said analog adder input end is electrically connected with said first input amplifier assembly output end and said second input amplifier assembly output end, and wherein said analog adder output end is electrically connected with said output end of said receiving circuit, and wherein said analog adder receives said first single-end output signal and said second single-end output signal, adds said first single-end output signal and said second single-end output signal to generate a resultant signal, and outputs said resultant signal to said output end of said receiving circuit.