Common mode sampling mechanism for residue amplifier in switched current pipeline analog-to-digital converters

A switched current pipeline analog-to-digital converter (ADC) integrated circuit, comprising:

• a track and hold circuit (T/H) configured to receive an analog input, to receive a T/H clock signal, and to generate a differential output of the T/H based on the analog input and the T/H clock signal;
• and
• a residue amplifier coupled to the T/H and configured to receive a reset clock signal, configured to receive the differential output of the T/H, configured to generate an input common mode signal from the differential output of the T/H, configured to generate a differential output of the residue amplifier, configured to generate an output common mode signal based on the differential output of the residue amplifier, configured to generate a common mode feedback signal based on a difference between the output common mode signal and a corrected input common mode signal, wherein the differential output of the residue amplifier is based on the differential output of the T/H and the common mode feedback signal, configured to generate a sample of the input common mode signal at a periodic rate of the reset clock signal and for a time duration that is less than half of a period of the reset clock signal, and configured to generate the corrected input common mode signal based on the sample of the input common mode signal.