Efficient calibration of errors in multi-stage analog-to-digital converter
AssigneeAnalog Devices, Inc.
InventorsCarroll C. Speir, Eric Otte, Jeffrey Paul Bray
Life of this patent
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AssigneeAnalog Devices, Inc.
InventorsCarroll C. Speir, Eric Otte, Jeffrey Paul Bray
Estimating the term…
Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.
A multi-stage analog-to-digital converter with digitally assisted calibration, the multi-stage analog-to-digital converter comprising:
A digitally assisted method for calibrating an analog-to-digital converter having multiple stages of analog-to-digital conversion, the method comprising:
An apparatus comprising:
A multi-stage converter with digitally assisted calibration, the multi-stage converter comprising:
Dependencies are inferred from the claim text.