Multiple split rail standard cell library architecture
AssigneeQUALCOMM Incorporated
InventorSatyanarayana Sahu
Life of this patent
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Abstract
A MOS device includes first and second sets of power rails. The first set of power rails extends across the MOS device and includes at least two power rails for providing a first voltage to the MOS device. The first set of power rails is interior to an edge of a cell boundary in the MOS device. At least one power rail of the first set of power rails extends over a pMOS active region of the MOS device. The second set of power rails extends across the MOS device and includes at least two power rails for providing a second voltage to the MOS device. The second set of power rails is interior to an edge of the cell boundary in the MOS device. At least one power rail of the second set of power rails extends over an nMOS active region of the MOS device.
Claims30
A metal oxide semiconductor (MOS) device, comprising:
- a first set of power rails extending in a first direction across the MOS device, the first set of power rails including at least two power rails for providing a first voltage to the MOS device, the first set of power rails being interior to an edge of a cell boundary in the MOS device with respect to a second direction orthogonal to the first direction, at least one power rail of the first set of power rails extending over a p-type MOS (pMOS) active region of the MOS device;
- and
- a second set of power rails extending in the first direction across the MOS device, the second set of power rails including at least two power rails for providing a second voltage to the MOS device, the second voltage being different than the first voltage, the second set of power rails being interior to an edge of the cell boundary in the MOS device with respect to the second direction, at least one power rail of the second set of power rails extending over an n-type MOS (nMOS) active region of the MOS device.
A method of operation of a metal oxide semiconductor (MOS) device, comprising:
- propagating a first voltage in a first set of power rails extending in a first direction across the MOS device, the first set of power rails including at least two power rails for providing the first voltage to the MOS device, the first set of power rails being interior to an edge of a cell boundary in the MOS device with respect to a second direction orthogonal to the first direction, at least one power rail of the first set of power rails extending over a p-type MOS (pMOS) active region of the MOS device;
- and
- propagating a second voltage in a second set of power rails extending in the first direction across the MOS device, the second set of power rails including at least two power rails for providing the second voltage to the MOS device, the second voltage being different than the first voltage, the second set of power rails being interior to an edge of the cell boundary in the MOS device with respect to the second direction, at least one power rail of the second set of power rails extending over an n-type MOS (nMOS) active region of the MOS device.
A metal oxide semiconductor (MOS) device, comprising:
- means for propagating a first voltage in a first set of power rails extending in a first direction across the MOS device, the first set of power rails including at least two power rails for providing the first voltage to the MOS device, the first set of power rails being interior to an edge of a cell boundary in the MOS device with respect to a second direction orthogonal to the first direction, at least one power rail of the first set of power rails extending over a p-type MOS (pMOS) active region of the MOS device;
- and
- means for propagating a second voltage in a second set of power rails extending in the first direction across the MOS device, the second set of power rails including at least two power rails for providing the second voltage to the MOS device, the second voltage being different than the first voltage, the second set of power rails being interior to an edge of the cell boundary in the MOS device with respect to the second direction, at least one power rail of the second set of power rails extending over an n-type MOS (nMOS) active region of the MOS device.
A computer-readable medium comprising design data corresponding to an apparatus, the apparatus comprising:
- a first set of power rails extending in a first direction across the MOS device, the first set of power rails including at least two power rails for providing a first voltage to the MOS device, the first set of power rails being interior to an edge of a cell boundary in the MOS device with respect to a second direction orthogonal to the first direction, at least one power rail of the first set of power rails extending over a p-type MOS (pMOS) active region of the MOS device;
- and
- a second set of power rails extending in the first direction across the MOS device, the second set of power rails including at least two power rails for providing a second voltage to the MOS device, the second voltage being different than the first voltage, the second set of power rails being interior to an edge of the cell boundary in the MOS device with respect to the second direction, at least one power rail of the second set of power rails extending over an n-type MOS (nMOS) active region of the MOS device.
Dependencies are inferred from the claim text.