Vertical gate all around (VGAA) transistors and methods of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChing-Hong Jiang, Li-Ting Wang, Teng-Chun Tsai, Shih-Chiang Chen
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Abstract
An embodiment method includes forming a nanowire extending upwards from a substrate, wherein the nanowire includes: a bottom semiconductor region; a middle semiconductor region over the bottom semiconductor region; and a top semiconductor region over the middle semiconductor region. The method also includes forming a dielectric layer around and extending over the nanowire and forming a chemical mechanical polish-stop (CMP-stop) layer within the dielectric layer using an implantation process. After forming the CMP-stop layer, the dielectric layer is planarized.
Claims20
A method of forming a vertical gate all around (VGAA) transistor, the method comprising:
- forming a nanowire extending upwards from a substrate, wherein the nanowire comprises:
- a bottom semiconductor region;
- a middle semiconductor region over the bottom semiconductor region;
- and
- a top semiconductor region over the middle semiconductor region;
- forming a dielectric layer around and extending over the nanowire;
- forming a chemical mechanical polish-stop (CMP-stop) layer within the dielectric layer using an implantation process, wherein the implantation process changes an etching rate of a portion of the dielectric layer;
- and
- after forming the CMP-stop layer, planarizing the dielectric layer.
A method of forming a vertical gate all around (VGAA) transistor,
- the method comprising:
- forming a dielectric layer around and extending above a nanowire;
- using a first implantation process to form a chemical mechanical polish-stop (CMP-stop) layer within the dielectric layer;
- planarizing the dielectric layer to remove an upper portion of the dielectric layer over the CMP-stop layer;
- using a second implantation process to form an etch-stop layer within the dielectric layer;
- and
- applying an etching process so that a top surface of the dielectric layer is substantially level with a surface of at least one source/drain region of the nanowire.
A method of forming a vertical gate all around (VGAA) transistor, the method comprising:
- forming a first dielectric layer over and extending along sidewalls of a nanowire, wherein the nanowire comprises:
- a bottom source/drain region;
- a channel region over the bottom source/drain region;
- and
- a top source/drain region over the channel region;
- implanting a first chemical mechanical polish-stop (CMP-stop) layer within the first dielectric layer;
- after implanting the first CMP-stop layer, planarizing the first dielectric layer;
- after planarizing the first dielectric layer, applying a first etching process so that a top surface of the first dielectric layer is substantially level with a top surface of the bottom source/drain region;
- forming a gate structure around the channel region;
- forming a second dielectric layer over the first dielectric layer and extending over the gate structure;
- implanting a second CMP-stop layer within the second dielectric layer;
- after implanting the second CMP-stop layer, planarizing the second dielectric layer;
- and
- after planarizing the second dielectric layer, applying a second etching process so that a top surface of the second dielectric layer is substantially level with a top surface of the channel region.
Dependencies are inferred from the claim text.