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US 9,501,601 B2Granted
Layout optimization of a main pattern and a cut pattern
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Ming Chang, Kuei-Liang Lu
Life of this patent
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Abstract
A method for feature pattern modification includes extracting both a main pattern and a cut pattern from a design pattern, the main pattern being laid out under a set of process guidelines that improve the process window during formation of the main pattern, and modifying at least one of: the main pattern and the cut pattern if either feature pattern is in violation of a layout rule.
Claims20
A method for pattern modification, the method comprising:
- with a computing system, extracting both a main pattern and a cut pattern from a design pattern, the main pattern being laid out under a set of process guidelines that improve a process window during formation of the main pattern;
- with the computing system, modifying at least one of:
- the main pattern and the cut pattern if either feature pattern is in violation of a layout rule;
- and
- with the computing system after modifying, in response to determining that the modifying enlarges the process window combining the main pattern and cut pattern to form a first modified pattern;
- and
- fabricating an integrated circuit based on the first modified pattern.
4 more elements
A computing system comprising:
- a processor;
- and a memory comprising computer readable instructions that when executed by the processor, cause the processor to:
- extract both a main pattern and a cut pattern from a design pattern, the main pattern being laid out under a set of process window rules that improve a process window during formation of the main pattern;
- and
- modify at least one of:
- the main pattern and the cut pattern if either feature pattern is in violation of a layout rule;
- and
- in response to determining that modification of at least one of the main pattern and the cut pattern enlarges the process window, create a final pattern;
- and
- causing a fabrication tool to fabricate an integrated circuit based on the final pattern.
7 more elements
A method for modifying a pattern of an integrated circuit device, the method comprising:
- with a computing system, separating the pattern into two portions:
- a first pattern portion and a second pattern portion;
- with the computing system, comparing the first pattern portion to a first set of layout rules, and comparing the second pattern portion to a second set of layout rules, wherein the first and second sets of layout rules apply different constraints to similar design features;
- with the computing system, modifying the first pattern portion to be in compliance with the first set of layout rules;
- with the computing system, after modifying, in response to determining that the modifying enlarges a process window, combining the first and second pattern portions to form a modified pattern;
- and
- fabricating an integrated circuit based on the modified pattern.
4 more elements
Dependencies are inferred from the claim text.