Secured comparison method of two operands and corresponding device

A device comprising:

• a processing unit coupled to a memory, wherein the processing unit is programmed to perform secure comparison of first and second initial operands each having b bits by:
• performing a first comparison operation of the first initial operand with the second initial operand using at least one comparison operator in such a way as to obtain a first final result word having p bits, wherein the first and second initial operands each have b bits and where p is less than b;
• performing a second comparison operation of the second initial operand with the first initial operand using the at least one comparison operator in such a way as to obtain a second final result word having p bits;
• and
• checking values of the bits of the first and second final result words in relation to a part of r combinations of reference values taken from 22p possible combinations of values of the first and second final result words, r being less than 22p, wherein the reference combination represent a valid result of comparison of the first and second initial operands including an equality, a relationship of inferiority and a relationship of superiority between the first and second initial operands;
• and
• control circuitry connected to the processing unit and configured to control operation of an integrated circuit according to contents of memory of a memory device at a location indicated by address information generated from the first and second final result words.

A device comprising:

• a first logic circuit configured to perform a first comparison operation of a first initial operand with a second initial operand using at least one comparison operator in such a way as to obtain a first final result word having p bits, wherein the first and second initial operands each have b bits and where p is less than b;
• a second logic circuit configured to perform a second comparison operation of the second initial operand with the first initial operand using the at least one comparison operator in such a way as to obtain a second final result word having p bits;
• a comparator configured to check the values of the bits of the first and second final result words in relation to a part of r combinations of reference values taken from 22p possible combinations of values of the first and second final result words, r being less than 22p, wherein the reference combination represent a valid result of comparison of the first and second initial operands including an equality, a relationship of inferiority and a relationship of superiority between the first and second initial operands;
• and
• control circuitry configured to control operation of an integrated circuit according to contents of memory of a memory device at a location indicated by address information generated from the first and second final result words.