E-beam inspection apparatus and method of using the same on various integrated circuit chips

An apparatus for detecting defects in an integrated circuit, wherein the integrated circuit includes a plurality of predetermined locations and the apparatus comprising:

• a target holder for holding said integrated circuit;
• an e-beam source that directs an e-beam toward each of the plurality of predetermined locations on the integrated circuit;
• a focusing column that accelerates the e-beam of electrons and separately, for each of the plurality of predetermined locations, focuses the e-beam to the plurality of predetermined locations, the focusing column including a condensor lens, an objective lens and a Wehnelt;
• a dual-deflection system that moves the e-beam over the integrated circuit to each of the plurality of predetermined locations, the dual deflection system including:
• a magnetic deflection component that provides by magnetic deflection for movement of the e-beam through a plurality of areas on the integrated circuit and placement of the e-beam at each of the plurality of areas, wherein each of the plurality of areas corresponds to a coarse field of view associated with the magnetic deflection component in a stationery state;
• and
• an electrostatic deflection component that provides by electrostatic deflection for movement of the e-beam within each of the plurality of areas and placement of the e-beam at each of particular ones of the plurality of predetermined locations located within a current one of the plurality of areas,
• a negative bias circuit that provides a negative bias between the objective lens and the target holder, the negative bias serving to (1) decelerate the e-beam so that the e-beam strikes the integrated circuit with a landing energy having a predetermined range, and (2) accelerate secondary electrons emitted from the integrated circuit;
• and
• a detector that detects a voltage contrast image of the secondary electrons emitted from the integrated circuit after the e-beam strikes each of the plurality of predetermined locations of the integrated circuit.