Power amplifier

A power amplifier comprising:

• n current sources (where “n” is a natural number equal to or greater than 3) that cause predetermined currents to flow;
• n switches that open and close current paths of the n current sources, respectively;
• a signal generating section that generates n timing signals for turning on/off the n switches, respectively;
• and
• one or more load adjustment MOS transistors that have a gate terminal coupled with a gate terminal of one or more MOS transistors having a smaller size than the other MOS transistors among the n MOS transistors, wherein:
• the n timing signals are signals that have an identical duty ratio and that are different in phase;
• the power amplifier outputs a signal amplified in power based on the currents flowing through the n current sources;
• the n switches are n MOS transistors;
• the n MOS transistors that are the n switches have constant channel lengths L, and channel widths W having sizes proportional to current values of the corresponding n current sources, respectively;
• the one or more load adjustment MOS transistors have drains and sources connected in a way that does not allow the currents to flow between the drains and the sources;
• and
• loads of the gate terminals of the n MOS transistors are made substantially equal to each other by addition of a gate load of the load adjustment MOS transistors.

A power amplifier comprising:

• n current sources (where “n” is a natural number equal to or greater than 3) that cause predetermined currents to flow;
• n switches that open and close current paths of the n current sources, respectively;
• and
• a signal generating section that generates n timing signals for turning on/off the n switches, respectively, wherein:
• the n timing signals are signals that have an identical duty ratio and that are different in phase;
• the power amplifier outputs a signal amplified in power based on the currents flowing through the n current sources;
• the n is an even number equal to or greater than 6;
• half of the n current sources, the n switches, and the n timing signals is categorized as a first group, and the remaining half thereof is categorized as a second group,
• the first group and the second group operate in opposite phases, and
• the power amplifier outputs a signal amplified in power based on a difference between a total current flowing through n/2 current sources in the first group and a total current flowing through n/2 current sources in the second group.

A power amplifier comprising:

• n current sources (where “n” is a natural number equal to or greater than 3) that cause predetermined currents to flow;
• n switches that open and close current paths of the n current sources, respectively;
• and
• a signal generating section that generates n timing signals for turning on/off the n switches, respectively;
• harmonic-wave-reduction current sources that cause predetermined currents to flow;
• harmonic-wave-reduction switches that open and close current paths of the harmonic-wave-reduction current sources;
• and
• a signal generating section that generates a harmonic-wave-reduction timing signal for turning on/off the harmonic-wave-reduction switches, wherein:
• the n timing signals are signals that have an identical duty ratio and that are different in phase;
• the power amplifier outputs a signal amplified in power based on the currents flowing through the n current sources;
• a frequency of the harmonic-wave-reduction timing signal is twice the frequency of the timing signals;
• and
• currents of the harmonic-wave-reduction current sources are added to an output of the power amplifier.