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AssigneeHuawei Technologies Co., Ltd.
InventorsTao Huang, Qifan Zhang, Wuxian Shi, Yiqun Ge, Wen Tong
Estimating the term…
A clock-less asynchronous processing circuit or system is configured to operation in a plurality of modes. In an initialization mode (e.g., reset, initialization, boot up), a self-clocked generator associated with the asynchronous circuit is configured to generate an active complete signal (to latch output processed data) within a first period of time after receiving a trigger signal. In a normal mode, the self-clocked generator is configured to generate the active complete signal within a second period of time after receiving the trigger signal. In one embodiment, during the initialization mode, the asynchronous circuit latches the output slower than when in the normal mode.
A clock-less asynchronous processing system, comprising:
A method of operating a clock-less asynchronous processing system comprising a processing pipeline having a plurality of successive processing stages, and a first processing stage further comprising, asynchronous logic circuitry, a data storage element coupled to an output of the asynchronous logic circuitry and a self-clocked generator, the method comprising:
A method for asynchronous processing within an asynchronous processor comprising an asynchronous logic circuit configured to receive input data and output processed data, the method comprising:
A clock-less asynchronous circuit, comprising:
Dependencies are inferred from the claim text.