Voltage level shifter module
AssigneeFreescale Semiconductor, Inc.
InventorAndrey Evgenevich Malkov
Life of this patent
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Abstract
A voltage level shifter module comprising at least one input arranged to receive an input signal, and at least one cascode transistor arranged to receive at a gate thereof at least one reference voltage signal. The voltage level shifter module further comprises at least one reference voltage control component arranged to detect logical state transitions within the input signal from at least a first logical state to a second logical state, and cause the reference voltage signal applied to the gate of the at least one cascode transistor to be pulled down to a reduced voltage upon detection of a logical state transition within the input signal from at least a first logical state to a second logical state.
Claims14
A voltage level shifter module comprising:
- at least one input arranged to receive an input signal;
- and
- at least one cascode transistor arranged to receive at a gate thereof at least one reference voltage signal;
- wherein the voltage level shifter module further comprises at least one reference voltage control component arranged to:
- detect logical state transitions within the input signal from at least a first logical state to a second logical state;
- cause the reference voltage signal applied to the gate of the cascode transistor to be pulled down to a reduced voltage upon detection of a logical state transition within the input signal from the first logical state to the second logical state;
- and
- wherein the reference voltage control component includes at least one of,
- an AND gate arranged to receive the input signal and an inverted form of the input signal and to output a first logic pulse upon the logical state transition;
- or
- a NAND gate arranged to receive the input signal and the inverted form of the input signal and to output a second logic pulse upon the logical state transition.
A method of controlling at least one reference voltage signal applied to a gate of at least one cascode transistor within a voltage level shifter module, the method comprising:
- receiving an input signal of the voltage level shifter module;
- detecting a logical state transition within the input signal of the voltage level shifter module;
- causing the at least one reference voltage signal to be pulled down to a reduced voltage upon detection of a logical state transition with the signal of the voltage level shifter module, and at least one of,
- receiving the input signal and an inverted form of the input signal at an AND gate and outputting a first logic pulse upon the logical state transition;
- or
- receiving the input signal and the inverted form of the input signal at a NAND gate and outputting a second logic pulse upon the logical state transition.
Dependencies are inferred from the claim text.