Semiconductor device and method of fabricating the same

A method of fabricating a semiconductor device, comprising:

• forming a peripheral circuit structure on a first substrate, wherein the peripheral circuit structure includes a peripheral transistor disposed on the first substrate and an interlayered insulating layer covering the peripheral transistor;
• forming a second substrate on the peripheral circuit structure, wherein the second substrate is formed of polysilicon;
• alternately and repeatedly stacking insulating layers and sacrificial layers on the second substrate to form a layered structure;
• forming a through hole penetrating the layered structure and at least a portion of the second substrate;
• and
• forming a semiconductor pattern in a lower region of the through hole to be in contact with the second substrate.

A semiconductor device, comprising:

• a peripheral circuit structure disposed on a first substrate, wherein the peripheral circuit structure includes a transistor, wherein a gate pattern of the transistor is disposed on the first substrate and a source/drain region of the transistor is formed in the first substrate;
• a second substrate disposed on the peripheral circuit structure, wherein the second substrate includes a common source region;
• a vertical semiconductor pattern including a lower semiconductor pattern and an upper semiconductor pattern, wherein the lower semiconductor pattern penetrates the second substrate, wherein a bottom surface of the lower semiconductor pattern is in contact with the peripheral circuit structure and a sidewall of the lower semiconductor pattern is in contact with the second substrate, wherein the upper semiconductor pattern is stacked on the lower semiconductor pattern;
• a plurality of gate electrodes disposed on a sidewall of the vertical semiconductor pattern;
• an electrode separation pattern disposed on the common source region of the second substrate, wherein the plurality of gate electrodes is interposed between the electrode separation pattern and the vertical semiconductor pattern;
• and
• a vertical insulator interposed between a sidewall of the vertical semiconductor pattern and at least one of the plurality of gate electrodes.