US 9,467,251 B2 · Method and system for forward error correction decoding with parity check for use in low complexity highly-spectrally efficient communications

Abstract

A receiver receives an inter-symbol correlated (ISC) signal with information symbols and a corresponding parity symbol. Values of information symbols are estimated utilizing parity samples that are generated from the parity symbols. One or more maximum likelihood (ML) decoding metrics are generated for the information symbols. One or more estimations are generated for the information symbols based on the one or more ML decoding metrics. A parity metric is generated for each of the one or more generated estimations of the information symbols. The parity metric is generated by summing a plurality of values of one of the generated estimations to generate a sum, and wrapping the sum to obtain a parity check value that is within the boundaries of a symbol constellation utilized in generating the information symbols.

Claims20

Dependent claims

A transmitter comprising:

a symbol mapper circuit configured to map a plurality of information bits to a plurality of information symbols of an output symbol stream;
a symbol-domain parity value insertion circuit configured to:
process said plurality of information symbols according to a parity function to generate a parity value;
and
add said parity value to said output symbol stream prior to said output symbol stream being transmitted onto a communication channel;
and
a transmitter front-end circuit configured to transmit the output symbol stream, after addition of the parity value, onto the communication channel.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/635,736Filed 2 Mar 2015 · continuation

Priority

20 Jun 2012

Published

US 2015/0270926 A124 Sep 2015

Granted

11 Oct 2016

Term ends

Not estimatedThe source records don’t support an estimate.

Classification49 codes

H04L 1/0041
By using forward error control: arrangements at the transmitter end
G06F 11/10
Error detection or correction by redundancy in data representation, e.g. by using checking codes: adding special bits or symbols to the coded…
H04B 1/0475
Circuits: with means for limiting noise, interference or distortion
H04B 1/10
Receivers: means associated with receiver for limiting or suppressing noise or interference

Family

Application61/662,085Us provisional application · filed 20 Jun 2012

Application61/726,099Us provisional application · filed 14 Nov 2012

Application61/729,774Us provisional application · filed 26 Nov 2012

Application61/747,132Us provisional application · filed 28 Dec 2012

Application13/755,060Parent of this continuation · filed 31 Jan 2013

Application14/057,098Parent of this continuation · filed 18 Oct 2013

US 8,566,687 B1Parent of this continuation · filed 22 Oct 2013

US 8,972,836 B2Parent of this continuation · filed 3 Mar 2015

US 2015/0270926 A1Pre-grant publication · published 24 Sep 2015

US 2014/0108892 A1Published application

US 9,467,251 B2This patent

From the US filing history. Foreign family members aren’t listed.

Method and system for forward error correction decoding with parity check for use in low complexity highly-spectrally efficient communications

Life of this patent

Method and system for forward error correction decoding with parity check for use in low complexity highly-spectrally efficient communications

Life of this patent

Abstract

Claims20