System and method to trim reference levels in a resistive memory

An apparatus comprising:

• a resistive memory reference array comprising multiple sets of reference cells;
• a reference resistance measurement circuit configured to measure a first effective reference resistance corresponding to a first set of reference cells and to measure a second effective reference resistance corresponding to a second set of reference cells;
• a trimming circuit configured to set a reference resistance based on the first effective reference resistance and the second effective reference resistance;
• and
• a write circuit coupled to the trimming circuit, the write circuit configured to modify one or more states of one or more magnetic tunnel junction devices corresponding to the first effective reference resistance in response to a determination that the first effective reference resistance is not substantially equal to an average effective reference resistance corresponding to the multiple sets of reference cells.

An apparatus comprising:

• means for storing multiple reference resistance values, the multiple reference resistance values arranged in multiple sets of reference cells;
• means for accessing a first set of reference cells to measure a first effective reference resistance corresponding to the first set of reference cells and for accessing a second set of reference cells to measure a second effective reference resistance corresponding to the second set of reference cells;
• means for setting a reference resistance based on the first effective reference resistance and the second effective reference resistance;
• and
• means for modifying one or more states of one or more magnetic tunnel junction devices corresponding to the first effective reference resistance in response to a determination by the means for setting that the first effective reference resistance is not substantially equal to an average effective reference resistance corresponding to the multiple sets of reference cells.

A computer readable storage device storing instructions that, when executed by a processor, cause the processor to perform operations comprising:

• at resistive memory device:
• initiating determining of an average effective reference resistance level based on a first effective reference resistance and a second effective reference resistance, the first effective reference resistance based on a first set of reference cells of the resistive memory device and the second effective reference resistance based on a second set of reference cells of the resistive memory device;
• and
• initiating trimming of a reference resistance at least partially based on the average effective reference resistance level, wherein trimming the reference resistance comprises, in response to determining that the first effective reference resistance is not substantially equal to the average effective reference resistance level, modifying one or more states of one or more magnetic tunnel junction devices associated with the first effective reference resistance.