# US 9,439,292 B1 · Method for manufacturing a circuit board with buried element having high density pin count and the circuit board structure

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- Number: US 9,439,292 B1
- Document ID: US9439292B1
- Status: Granted
- Kind: B1
- Application number: 14/641,016
- Filed: 2015-03-06
- Published: 2016-09-08
- Granted: 2016-09-06
- Earliest claimed: 2015-03-06
- Assignees: Kinsus Interconnect Technology Corp.
- Applicants: Kinsus Interconnect Technology Corp.
- Inventors: Ting-Hao Lin; Yi-Fan Kao; Jaen-Don Lan; Yung-Lin Chia; An-Ping Tseng
- Web page: https://patentgrep.com/patent/US9439292B1

## CPC

- H05K 3/064: {Photoresists}
- H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
- H05K 1/188: {manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/00: Interconnections or connectors in packages
- H05K 3/0008: {for aligning or positioning of tools relative to the circuit board (H05K3/4638, H05K3/4679 take precedence; for manufacturing assemblages of components H05K13/0015)}
- H05K 3/108: {by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241)}
- H05K 3/305: {Affixing by adhesive}
- H05K 3/425: {characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern}
- H05K 2201/09563: Metal filled via
- H05K 2201/10674: Flip chip
- H05K 2203/166: Alignment or registration; Control of registration
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a circuit board with a buried element having high density pin count, wherein a micro copper window formed in a first circuit by patterned dry film electroplating is easily controlled less than 50 μm so that the micro conduction holes formed after the laser drilling each has a diameter greatly shrunk less than 50 μm so as to highly increase density of the micro conduction holes, thereby facilitating in burial of the buried element with the high density pin count. Additionally, by disposing the micro conduction holes in the same elevation, optically aligning a fixing position for the buried element can be controlled precisely.

## Claims

### Claim 1

A method for manufacturing a circuit board with buried high density pins, comprising:
electroplating a carrier plate such that a first metal layer is formed on said carrier plate;
forming a first circuit on one side surface of said first metal layer, wherein said first circuit includes a plurality of copper pads;
covering a photoresist layer over said first metal layer and said first circuit;
patterning said photoresist layer such that only said first circuit is covered by said photoresist layer after the patterning process;
etching said first metal layer covered by remaining portions of said photoresist layer, thereby removing said photoresist layer entirely;
providing an adhesive layer between some of said copper pads and a buried element in order to fix said buried element over said adhesive layer, wherein said buried element has a plurality of high density I/O (Input/Output) pins, each is aligned with a micro copper window defined between an adjacent pair of said copper pads and is staggered with a copper window defined by one of said copper pads adjacent to said micro copper window, wherein establish said copper window as a target point;
sequentially forming an insulating layer and a second metal layer over said first circuit and said buried element and removing said carrier plate and etching said first metal layer until said adhesive layer is exposed from said first metal layer via said micro copper window while said insulating layer is exposed from said first metal layer via said copper window;
optically aligning said target point and employing a drilling process to drill through the insulation layer between corresponding pair of said I/O pin and said micro copper window so as to form a micro through hole in alignment with said I/O pin and a through hole extending through said insulating layer and said second metal layer and in alignment with said copper window;
electroplating to form a conduction layer which covers said micro through hole and said through hole; and
etching said conduction layer in order to remove portions of said first metal layer until exposing said first circuit and simultaneously forming a plurality of micro conduction holes and a plurality of conduction holes for establishing electrical communication between said I/O pins of said buried element with said micro conduction holes and said conduction holes.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein said carrier plate is fabricated from metal material.

### Claim 3 (depends on 1)

The method as claimed in claim 1, wherein said first circuit is formed by a process of patterned dry film electroplating.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein said photoresist layer is in form of a dry film photoresist or a wet film photoresist.

### Claim 5 (depends on 1)

The method as claimed in claim 1, wherein mounting of said buried element is conducted based on said target point.

### Claim 6 (depends on 1)

The method as claimed in claim 1, wherein said buried element is in form of an active element or a passive element.

### Claim 7 (depends on 1)

The method as claimed in claim 1, wherein said adhesive layer is fabricated via epoxy dispensing technique, screen printing or sequentially lamination process in form a sheet or roll and is laminated on said first circuit, wherein said adhesive layer has an opening aligned with said copper window being filled by said conduction hole.

### Claim 8 (depends on 1)

The method as claimed in claim 1, wherein said drilling process is a laser drilling process.

### Claim 9 (depends on 1)

The method as claimed in claim 1, wherein each of said micro conduction holes is a blind via hole or a buried via hole.

### Claim 10

A circuit board structure with buried high density pin, comprising:
an insulating layer;
at least one first circuit buried within said insulating layer;
a second circuit formed exterior of said insulating layer;
an adhesive layer and a buried element respectively buried within said insulating layer such that said buried element is located above said adhesive layer, wherein said buried element has a plurality of high density Input/Output (I/O) pins disposed within said adhesive layer so as to define a plurality of micro conduction holes, portions of said first circuit located outside of said insulating layer cooperating with said second circuit to define a plurality of a plurality of conduction holes.