# US 9,438,844 B2 · Video multiviewer system using direct memory access (DMA) registers and block RAM > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,844 B2 - Document ID: US9438844B2 - Status: Granted - Kind: B2 - Application number: 12/099,380 - Filed: 2008-04-08 - Published: 2009-10-08 - Granted: 2016-09-06 - Earliest claimed: 2008-04-08 - Assignees: Imagine Communications Corp. - Applicants: Cristian Camer; Marcin Komorowski - Inventors: Cristian Camer; Marcin Komorowski - Web page: https://patentgrep.com/patent/US9438844B2 ## CPC - H04N 21/47: End-user applications - G09G 5/001: {Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor} - G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)} - G09G 5/14: Display of multiple viewports - G09G 5/363: {Graphics controllers} - G09G 5/397: Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay (G09G5/02 takes precedence) - H04N 5/44504: {Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits} - H04N 21/426: Internal components of the client {; Characteristics thereof} (H04N5/44 takes precedence) - H04N 21/42653: {for processing graphics} - H04N 21/4316: {for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window} - H04N 21/440263: {by altering the spatial resolution, e.g. for displaying on a connected PDA} - G09G 2340/0407: Resolution change, inclusive of the use of different resolutions for different screen areas - G09G 2352/00: Parallel handling of streams of display data - G09G 2360/126: The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM - G09G 2370/10: Use of a protocol of communication by packets in interfaces along the display data pipeline - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A video multiviewer system includes a Graphics Processing Unit (GPU) that includes a GPU memory. A video input module is operative with the GPU for receiving video data and transferring the video data to the GPU memory via a Direct Memory Access (DMA). A programmable circuit such as a Field Programmable Gate Array (FPGA) includes a multi-ported and in one aspect a dual ported block Random Access Memory (RAM) configured for a plurality of DMA channels for receiving video data and allowing uninterrupted operation of consecutive DMA transfers of video data to the GPU memory. A display displays the multiple video windows based upon video data received within the GPU memory. ## Claims ### Claim 1 A video multiviewer system comprising: a graphics processing unit (GPU) comprising a GPU memory; a Direct Memory Access (DMA) controller; a video input module configured to receive simultaneously a plurality of video streams corresponding to video data and transfer the video data to the GPU memory via DMA, wherein the video input module comprises a programmable circuit having dual-ported Block Random Access Memory (RAM) comprising first and second ports, wherein the first port is operative with a host and the second port is operative with the DMA controller, wherein the dual-ported Block RAM is configured with a plurality of DMA channels for receiving the video data based on a number of plurality of video streams received at the video input module and is further configured to allow uninterrupted operation of consecutive DMA transfers of the video data to the GPU memory, wherein the first port is configured to allow independent read/write access by the host for configuration of the plurality of DMA channels using the first port, and the second port is configured to access video data in the plurality of DMA channels using simultaneous read/write access by DMA controller through the second port; and a display configured to receive the video data stored at the GPU memory and simultaneously present multiple video streams in respective windows of the display. ### Claim 2 (depends on 1) The video multiviewer system according to claim 1, and further comprising a Read/Write controller and plurality of registers, wherein as the DMA controller operates on DMA channel “n,” the Read/Write controller is operative for pre-reading registers for DMA channel “n+1”. ### Claim 3 (depends on 2) The video multiviewer system according to claim 2, wherein the DMA controller changes state variables in registers when the video data is transferred within DMA channel “n”. ### Claim 4 (depends on 2) The video multiviewer system according to claim 2, wherein the DMA controller is operative for modifying the video data within registers and passing the video data back to the Read/Write controller to be stored back within the dual-ported Block RAM. ### Claim 5 (depends on 1) The video multiviewer system according to claim 1, and further comprising a video data controller operative with the video input module for assigning addresses to be used for the video data within the GPU memory. ### Claim 6 (depends on 1) The video multiviewer system according to claim 1, and further comprising a plurality of video scalers operating in parallel for generating initially scaled video data by performing video scaling in at least one dimension on the plurality of video streams. ### Claim 7 A video multiviewer system comprising: a graphics processing unit (GPU) comprising a GPU memory; a Direct Memory Access (DMA) controller; a Read/Write controller; a video input module configured to receive simultaneously a plurality of video streams corresponding to video data and transfer the video data to the GPU memory via DMA, wherein the video input module comprises a Field Programmable Gate Array (FPGA) comprising a dual ported Block Random Access Memory (RAM) comprising Pre-read registers, Write Back registers and Working registers, and further comprising first and second ports, wherein the dual-ported Block RAM is configured with a plurality of DMA channels for receiving the video data based on a number of plurality of video streams received at the video input module, wherein the first port is operative with a host and the second port is operative with the DMA controller, wherein the DMA controller and the Read/Write controller are operative together with the Pre-read registers, Write Back registers and Working registers for receiving the video data and allowing uninterrupted operation of consecutive DMA transfers of the video data to the GPU memory, wherein the first port is configured to allow independent read/write access by the host for configuration of the plurality of DMA channels through the first port, and the second port is configured to access the video data of the plurality of DMA channels using simultaneous read/write access by the DMA controller through the second port; and a display configured to receive the video data stored at the GPU memory and simultaneously present video streams in respective windows of the display. ### Claim 8 (depends on 7) The video multiviewer system according to claim 7, wherein as the DMA controller operates on DMA channel “n,” the Read/Write controller is operative for pre-reading registers for DMA channel “n+1. ### Claim 9 (depends on 7) The video multiviewer system according to claim 7, wherein the DMA controller changes state variables in registers when the video data is transferred within DMA channel “n”. ### Claim 10 (depends on 7) The video multiviewer system according to claim 7, wherein the DMA controller is operative for modifying the video data and passing the video data back to the Read/Write controller to be stored back the dual-ported Block RAM. ### Claim 11 (depends on 7) The video multiviewer system according to claim 7, and further comprising a video data controller operative with the video input module for assigning addresses to be used for the video data within the GPU memory. ### Claim 12 (depends on 7) The video multiviewer system according to claim 7, and further comprising a plurality of video scalers operating in parallel for generating initially scaled video data by performing video scaling in at least one dimension on the plurality of video streams. ### Claim 13 A method for displaying multiple video windows on a video multiviewer display, comprising: receiving, at a video input module, simultaneously a plurality of video streams corresponding to video data, wherein the video input module is coupled to a Graphics Processing Unit (GPU) having a GPU memory and further coupled to a DMA controller; transferring the video data to the GPU memory via DMA through a programmable circuit having a dual ported Block Random Access Memory (RAM) comprising first and second ports, wherein the first port is operative with a host and the second port is operative with the DMA controller, wherein the dual-ported Block RAM is configured with a plurality of DMA channels for receiving the video data based on a number of plurality of video streams received at the video input module and is further configured to allow uninterrupted operation of consecutive DMA transfers of the video data to the GPU memory, wherein the first port is configured to allow independent read/write access by the host for configuration of the plurality of DMA channels through the first port, and the second port is configured to access video data in the plurality of DMA channels using simultaneous read/write access by the DMA controller through the second port; receiving, at a display, the video data stored at the GPU memory; and presenting simultaneously video streams in respective windows. ### Claim 14 (depends on 13) The method according to claim 13, which further comprises operating on DMA channel “n” with the DMA controller while the Read/Write controller pre-reads registers for DMA channel “n+1”. ### Claim 15 (depends on 13) The method according to claim 13, which further comprises changing state variables in registers while transferring the video data within DMA channel “n”. ### Claim 16 (depends on 13) The method according to claim 13, which further comprises modifying the video data within registers and passing the video data back to the Read/Write controller to be stored back within the dual-ported Block RAM. ### Claim 17 (depends on 13) The method according to claim 13, which further comprises assigning addresses for the video data within the GPU memory. ### Claim 18 (depends on 13) The method according to claim 13, which further comprises scaling the video data within a plurality of video scalers operating in parallel and generating initially scaled video data by performing video scaling in at least one dimension on the plurality of video streams.