# US 9,438,841 B2 · Solid-state imaging apparatus and imaging system

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- Number: US 9,438,841 B2
- Document ID: US9438841B2
- Status: Granted
- Kind: B2
- Application number: 15/013,185
- Filed: 2016-02-02
- Published: 2016-06-02
- Granted: 2016-09-06
- Earliest claimed: 2013-09-17
- Assignees: Canon Kabushiki Kaisha
- Applicants: Canon Kabushiki Kaisha
- Inventors: Kazuo Yamazaki; Tetsuya Itano; Hiroki Hiyama
- Web page: https://patentgrep.com/patent/US9438841B2

## CPC

- H04N 25/778: comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
- H04N 25/616: involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
- H04N 25/65: applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A solid-state imaging apparatus includes a pixel section in which a plurality of pixels are arranged in a matrix, a column signal line configured to output a pixel signal from the pixel section, a column amplifier circuit configured to invert and amplify the pixel signal, a bypass circuit configured to bypass the column amplifier circuit, an AD converter, and a control unit configured to change an operation mode of the AD converter in accordance with the operation of the bypass circuit.

## Claims

### Claim 1

A solid-state imaging apparatus comprising:
a pixel section in which a plurality of pixels are arranged in a matrix;
a column signal line configured to output a pixel signal from the pixel section;
a column amplifier circuit configured to output an amplified signal by inverting and amplifying the pixel signal;
a bypass circuit configured to bypass the column amplifier circuit;
a successive approximation analogue to digital (AD) converter;
a correlated double sampling (CDS) processing unit configured to calculate a difference between a reset level of the pixel signal and an imaging signal; and
a control unit configured to change an operation mode of the successive approximation AD converter,
wherein the control unit is configured to:
in a first operation mode, to control the successive approximation AD converter to AD-convert the pixel signal from the column signal line via the bypass circuit,
in a second operation mode, to control the successive approximation AD converter to AD-convert the amplified signal, and
to change differential processing of the CDS processing unit between the first operation mode and the second operation mode.

### Claim 2 (depends on 1)

The apparatus according to claim 1, wherein the CDS processing unit is configured to:
in the first operation mode, among the reset level of the pixel signal and the imaging signal, to subtract one signal from an other signal,
in the second operation mode, among the reset level of the pixel signal and the imaging signal, to subtract the other signal from the one signal.

### Claim 3 (depends on 1)

The apparatus according to claim 1, further comprising a column selection circuit configured to transfer, to a digital processing circuit, a signal for each column output from the successive approximation AD converter,
wherein the digital processing circuit is configured to process the transferred signal,
wherein the digital processing circuit includes the CDS processing unit to calculate the difference between the reset level of the pixel signal and the imaging signal.

### Claim 4 (depends on 1)

The apparatus according to claim 1, wherein in the first operation mode, the reset level of the pixel signal and the imaging signal are outputted via the bypass circuit, and in the second operation mode, the reset level of the pixel signal and the imaging signal are amplified and outputted by the column amplifier circuit.

### Claim 5

An imaging system comprising:
a solid-state imaging apparatus;
an optical system configured to form an image on the solid-state imaging apparatus; and
a signal processing circuit configured to process an output signal from the solid-state imaging apparatus,
the solid-state imaging apparatus comprising:
a pixel section in which a plurality of pixels are arranged in a matrix;
a column signal line configured to output a pixel signal from the pixel section;
a column amplifier circuit configured to output an amplified signal by inverting and amplifying the pixel signal;
a bypass circuit configured to bypass the column amplifier circuit;
a successive approximation analogue to digital (AD) converter;
a correlated double sampling (CDS) processing unit configured to calculate a difference between a reset level of the pixel signal and an imaging signal; and
a control unit configured to change an operation mode of the successive approximation AD converter and the CDS processing unit,
wherein the control unit is configured to:
in a first operation mode, to control the successive approximation AD converter to AD-convert the pixel signal output from the column signal line via the bypass circuit,
in a second operation mode, to control the successive approximation AD converter to AD-convert the amplified signal, and
to change differential processing of the CDS processing unit between the first operation mode and the second operation mode.