# US 9,438,820 B1 · Systems and methods for processing composite video signals

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- Number: US 9,438,820 B1
- Document ID: US9438820B1
- Status: Granted
- Kind: B1
- Application number: 14/613,638
- Filed: 2015-02-04
- Granted: 2016-09-06
- Earliest claimed: 2014-02-04
- Assignees: Marvell International Ltd.
- Applicants: Marvell International Ltd.
- Inventors: Yichen Liu; Hongyu Zhang; Wei Zheng; Yanwei Ji
- Web page: https://patentgrep.com/patent/US9438820B1

## CPC

- H04N 5/06: Generation of synchronising signals
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

System and methods are provided for processing composite video signals. The system includes: a clock synthesizer configured to generate a line lock clock signal; an interpolation unit configured to generate source data associated with a source composite video signal, the source composite video signal being related to a source clock signal; a buffer unit configured to store the source data based at least in part on the source clock signal and provide destination data based at least in part on the line lock clock signal; a signal processing unit configured to process the destination data to extract a synchronization component and determine a phase error between the synchronization component and the line lock clock signal. The clock synthesizer is further configured to adjust the line lock clock signal based at least in part on the phase error.

## Claims

### Claim 1

A system for processing composite video signals, the system comprising:
a clock synthesizer configured to generate a line lock clock signal;
an interpolation unit configured to generate source data associated with a source composite video signal, the source composite video signal being related to a source clock signal;
a buffer unit configured to store the source data based at least in part on the source clock signal and provide destination data based at least in part on the line lock clock signal;
a signal processing unit configured to process the destination data to extract a synchronization component and determine a phase error between the synchronization component and the line lock clock signal;
the clock synthesizer being further configured to adjust the line lock clock signal based at least in part on the phase error, and
the interpolation unit being further configured to adjust the source data based at least in part on the phase error.

### Claim 2 (depends on 1)

The system of claim 1, wherein:
the signal processing unit includes: a loop filter configured to generate a control signal based at least in part on the phase error, and
the clock synthesizer is further configured to adjust the line lock clock signal based at least in part on the control signal.

### Claim 3 (depends on 1)

The system of claim 1, further comprising:
a phase-information generator configured to provide phase information to the interpolation unit;
wherein the interpolation unit is further configured to generate the source data by interpolating the source composite video signal based at least in part on the phase information.

### Claim 4 (depends on 3)

The system of claim 3, wherein:
the phase-information generator is further configured to provide a valid signal to the interpolation unit;
wherein the buffer unit is further configured to store the source data when the valid signal is at a logic high level.

### Claim 5 (depends on 4)

The system of claim 4, wherein:
the signal processing unit includes: a loop filter configured to generate a control signal based at least in part on the phase error, and
the phase-information generator is further configured to adjust the phase information and the valid signal based at least in part on the control signal.

### Claim 6 (depends on 1)

The system of claim 1, wherein the clock synthesizer is further configured to adjust the line lock clock signal to reduce the phase error between the synchronization component and the line lock clock signal.

### Claim 7 (depends on 1)

The system of claim 1, wherein the buffer unit is further configured to output the destination data when the stored source data reaches a threshold.

### Claim 8 (depends on 1)

The system of claim 1, wherein the interpolation unit includes a time-dependent finite impulse response filter.

### Claim 9 (depends on 1)

The system of claim 1, wherein the signal processing unit includes:
an error detector configured to extract the synchronization component and determine the phase error between the synchronization component and the line lock clock signal.

### Claim 10 (depends on 9)

The system of claim 9, wherein the synchronization component corresponds to one or more pulses in the source composite video signal.

### Claim 11 (depends on 1)

The system of claim 1, wherein the signal processing unit includes: a pre-filter configured to remove high frequency noise from the destination data.

### Claim 12

A method for processing composite video signals, the method comprising:
generating a line lock clock signal;
generating source data associated with a source composite video signal, the source composite video signal being related to a source clock signal;
storing the source data in a buffer based at least in part on the source clock signal;
providing destination data from the buffer based at least in part on the line lock clock signal;
processing the destination data to extract a synchronization component;
determining a phase error between the synchronization component and the line lock clock signal;
adjusting the line lock clock signal based at least in part on the phase error; and
adjusting the source data based at least in part on the phase error.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
generating a control signal based at least in part on the phase error; and
adjusting the line lock clock signal based at least in part on the control signal.

### Claim 14 (depends on 12)

The method of claim 12, further comprising:
generating phase information; and
interpolating the source composite video signal based at least in part on the phase information to generate the source data.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
providing a valid signal;
wherein the source data is stored to the buffer when the valid signal is at a logic high level.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
generating a control signal based at least in part on the phase error; and
adjusting the phase information and the valid signal based at least in part on the control signal.

### Claim 17 (depends on 12)

The method of claim 12, further comprising:
adjusting the line lock clock signal to reduce the phase error between the synchronization component and the line lock clock signal.

### Claim 18 (depends on 12)

The method of claim 12, wherein the destination data is output from the buffer when the stored source data reaches a threshold.

### Claim 19 (depends on 12)

The method of claim 12, wherein the synchronization component corresponds to one or more pulses in the source composite video signal.

### Claim 20

A system for processing composite video signals, the system comprising:
one or more data processors; and
a computer-readable storage medium encoded with instructions for commanding the data processors to execute operations including:
generating a line lock clock signal;
generating source data associated with a source composite video signal, the source composite video signal being related to a source clock signal;
storing the source data in a buffer based at least in part on the source clock signal;
providing destination data from the buffer based at least in part on the line lock clock signal;
processing the destination data to extract a synchronization component;
determining a phase error between the synchronization component and the line lock clock signal;
adjusting the line lock clock signal based at least in part on the phase error; and
adjusting the source data based at least in part on the phase error.