# US 9,438,539 B1 · Apparatus and method for optimizing the number of accesses to page-reference count storage in page link list based switches

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- Number: US 9,438,539 B1
- Document ID: US9438539B1
- Status: Granted
- Kind: B1
- Application number: 14/142,631
- Filed: 2013-12-27
- Granted: 2016-09-06
- Earliest claimed: 2013-09-03
- Assignees: Xpliant, Inc.
- Applicants: Xpliant, Inc.
- Inventors: Tsahi Daniel; Enric Musoll; Sridevi Polasanapalli
- Web page: https://patentgrep.com/patent/US9438539B1

## CPC

- H04L 69/22: Parsing or analysis of headers
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A packet processor includes a packet memory manager configured to receive a single header reference count and a single payload reference count for a packet. A page link list walk for the header under the control of the header reference count is performed in parallel with a page link list walk for the payload under the control of the payload reference count.

## Claims

### Claim 1

A packet processor, comprising:
a packet memory manager configured to
receive a single header reference count and a single payload reference count for a packet with a header and a payload; and
perform in parallel a page link list walk for the header under the control of the single header reference count and a page link list walk for the payload under the control of the single payload reference count, wherein each page link list walk traverses a linked list of all pages that a particular packet uses in packet memory.

### Claim 2 (depends on 1)

The packet processor of claim 1 wherein the single header reference count is associated with a first header page for the packet.

### Claim 3 (depends on 1)

The packet processor of claim 1 wherein the single payload reference count is associated with a first payload page for the packet.

### Claim 4 (depends on 1)

The packet processor of claim 1 wherein the packet memory manager is configured to process a payload valid indication.

### Claim 5 (depends on 1)

The packet processor of claim 1 wherein the packet memory manager is configured to free a page when the single payload reference count is one.

### Claim 6 (depends on 1)

The packet processor of claim 1 wherein the packet memory manager is configured to free individual pages after a first reference page is recycled.

### Claim 7 (depends on 1)

The packet processor of claim 1 further comprising:
a packet memory manager configured to
receive an indicator of reference count invalidity; and
free a header page and a payload page in response to the indication of reference count invalidity without accessing a reference count.