# US 9,438,536 B2 · 50 Gb/s Ethernet using serializer/deserializer lanes > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,536 B2 - Document ID: US9438536B2 - Status: Granted - Kind: B2 - Application number: 14/789,580 - Filed: 2015-07-01 - Published: 2015-10-22 - Granted: 2016-09-06 - Earliest claimed: 2012-07-16 - Assignees: Broadcom Corporation - Applicants: Broadcom Corporation - Inventors: Burhan Masood; Howard Frazier - Web page: https://patentgrep.com/patent/US9438536B2 ## CPC - H04L 49/352: {Gigabit ethernet switching [GBPS]} - G06F 13/00: Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor G06F9/46}; multiprocessor systems G06F15/16 ) - H04L 12/18: for broadcast or conference {, e.g. multicast} - H04L 12/4013: {Management of data rate on the bus (systems modifying transmission characteristics according to link quality H04L1/0001)} - H04L 45/16: Multipoint routing - H04L 45/44: Distributed routing - H04L 49/00: Packet switching elements - H04L 49/25: Routing or path finding in a switch fabric - H04L 49/351: for local area network [LAN], e.g. Ethernet switches - Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serial/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate. ## Claims ### Claim 1 A device comprising: circuitry configured to receive Ethernet frames on each of a plurality of serializer/deserializer (SERDES) lanes at a M/N Gb/s rate, where M is a value greater than or equal to 10 and N is a number of the SERDES lanes; bond the SERDES lanes into a stream of received Ethernet frames; and provide data from the bonded stream of Ethernet frames to a MAC port having an M Gb/s rate. ### Claim 2 (depends on 1) The device of claim 1, wherein each of the plurality of SERDES lanes are associated with a single port. ### Claim 3 (depends on 1) The device of claim 1, wherein the circuitry is configured to demultiplex the Ethernet frames received on each of the plurality of SERDES lanes. ### Claim 4 (depends on 1) The device of claim 1, wherein the circuitry is configured to demultiplex the Ethernet frames received on each of the plurality of SERDES lanes to a plurality of Physical Coding Sublayer (PCS) lanes. ### Claim 5 (depends on 4) The device of claim 4, wherein the circuitry is configured to align the plurality of PCS lanes. ### Claim 6 (depends on 4) The device of claim 4, wherein the circuitry is configured to align the plurality of PCS lanes using alignment markers included in blocks that encode the Ethernet frames. ### Claim 7 (depends on 6) The device of claim 6, wherein the circuitry is configured to remove the alignment markers after aligning the plurality of PCS lanes. ### Claim 8 (depends on 7) The device of claim 7, wherein the circuitry is configured to bond the aligned plurality of PCS lanes after the alignment markers have been removed to form the stream of received Ethernet frames. ### Claim 9 (depends on 1) The device of claim 1, M is 50. ### Claim 10 (depends on 1) The device of claim 1, wherein N is 2 or 4. ### Claim 11 (depends on 1) The device of claim 1, wherein the plurality of SERDES lanes are arranged to electrically couple to a corresponding plurality of SERDES lanes on a midplane of a blade server chassis. ### Claim 12 (depends on 11) The device of claim 11, wherein each of the SERDES lanes on the midplane is associated with an electrical trace group on the midplane. ### Claim 13 (depends on 12) The device of claim 12, wherein each of electrical trace group includes a transmit differential pair and a receive differential pair. ### Claim 14 (depends on 1) The device of claim 1, wherein the received Ethernet frames are distributed across the plurality of SERDES lanes using Multi-Lane Distribution across a plurality of Physical Coding Sublayer (PCS) lanes. ### Claim 15 (depends on 1) The device of claim 1, wherein the device is configured to support another link rate lower than M Gb/s and to autonegotiate between the link rates. ### Claim 16 (depends on 15) The device of claim 15, wherein the autonegotiation is conducted on a lane 0 of the SERDES lanes. ### Claim 17 (depends on 15) The device of claim 15, wherein the autonegotiation is conducted in accordance with IEEE 802.3an. ### Claim 18 A method comprising: receiving Ethernet frames on each of a plurality of serializer/deserializer (SERDES) lanes at a M/N Gb/s rate, where M is a value greater than or equal to 10 and N is a number of the SERDES lanes; bonding the SERDES lanes into a stream of received Ethernet frames; and providing data from the bonded stream of Ethernet frames to a MAC port having an M Gb/s rate. ### Claim 19 (depends on 18) The method of claim 18, further comprising: demultiplexing the Ethernet frames received on each of the plurality of SERDES lanes to a plurality of Physical Coding Sublayer (PCS) lanes; align the plurality of PCS lanes using alignment markers included in blocks that encode the Ethernet frames; and remove the alignment markers after aligning the plurality of PCS lanes. ### Claim 20 A device comprising circuitry configured to generate Ethernet frames from data received at a media access control (MAC) interface associated with a port having an M Gb/s link rate, M being a value greater than or equal to 10; distribute the Ethernet frames across a group of serializer/deserializer (SERDES) lanes associated with the port, the group having a size N which is greater than 1; transmit the distributed Ethernet frames on each of the SERDES lanes at an M/N Gb/s rate; receive Ethernet frames on each of the SERDES lanes at a M/N Gb/s rate; bond the SERDES lanes into a stream of received Ethernet frames; and provide data from the bonded stream of Ethernet frames to the MAC port at an M Gb/s rate.