# US 9,438,410 B2 · Semiconductor apparatus and system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,410 B2 - Document ID: US9438410B2 - Status: Granted - Kind: B2 - Application number: 14/673,168 - Filed: 2015-03-30 - Published: 2016-06-16 - Granted: 2016-09-06 - Earliest claimed: 2014-12-15 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jung Hwan Lee - Web page: https://patentgrep.com/patent/US9438410B2 ## CPC - H04L 7/0091: {Transmitter details} - H03K 3/037: Bistable circuits - H03K 3/356: Bistable circuits - H03K 3/356026: {with synchronous operation (H03K3/356034, H03K3/356052 take precedence)} - H03K 3/356121: {with synchronous operation (H03K3/35613, H03K3/356147 take precedence)} - H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines} - H04L 7/04: Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} - H04L 25/49: using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A semiconductor apparatus includes a transmission block and a reception block. The transmission block may convert an input signal into two or more synchronization signals, some bits of which have longer data valid windows than the other bits, and output the two or more synchronization signals. The reception block may generate the output signal by capturing bits having longer data valid windows between the two or more synchronization signals. ## Claims ### Claim 1 A semiconductor apparatus comprising: a transmission block configured to convert an input signal into two or more synchronization signals, some bits of which have longer data valid windows than the other bits, and output the two or more synchronization signals; and a reception block configured to generate the output signal by capturing bits having longer data valid windows between the two or more synchronization signals, wherein the transmission block alternately outputs the some bits and the other bits in series, wherein the transmission block is configured to convert the input signal into a rising synchronization signal and a falling synchronization signal, and output the rising synchronization signal, a first bit of which has a longer data valid window than a second bit, and the falling synchronization signal, a second bit of which has a longer data valid window than a first bit, and the reception block is configured to output the rising synchronization signal as an output signal by capturing the first bit, and output the falling synchronization signal as the output signal by capturing the second bit. ### Claim 2 (depends on 1) The semiconductor apparatus according to claim 1, wherein the transmission block comprises: a clock generation unit configured to receive the clock, and generate a falling clock and a rising clock; a first latch unit configured to receive and store the input signal during a high period of the falling clock, and output the rising synchronization signal; and a second latch unit configured to receive and store the input signal during a high period of the rising clock, and output the falling synchronization signal. ### Claim 3 (depends on 2) The semiconductor apparatus according to claim 2, wherein a phase of the falling clock and a phase of the rising clock are opposite to each other. ### Claim 4 (depends on 2) The semiconductor apparatus according to claim 2, wherein the first latch unit receives and stores the input signal having a certain logic level during the high period of the falling clock, and retains the logic level of the stored signal during a low period of the falling clock. ### Claim 5 (depends on 2) The semiconductor apparatus according to claim 2, wherein the second latch unit receives and stores the input signal having a certain logic level during the high period of the rising clock, and retains the logic level of the stored signal during a low period of the rising clock. ### Claim 6 (depends on 1) The semiconductor apparatus according to claim 1, wherein the reception block receives the rising synchronization signal during the high period of the rising clock, and outputs the output signal, and wherein the reception block receives the falling synchronization signal during the high period of the falling clock, and outputs the output signal. ### Claim 7 (depends on 1) The semiconductor apparatus according to claim 1, wherein the transmission block comprises: a splitter configured to receive the clock, and generate a rising clock and a falling clock; a first latch unit configured to generate the rising synchronization signal by receiving and storing the input signal during a high period of the falling clock and retaining a latched signal during a low period of the falling clock; and a second latch unit configured to generate the falling synchronization signal by receiving and storing the input signal during a high period of the rising clock and retaining a latched signal during a low period of the rising clock. ### Claim 8 (depends on 7) The semiconductor apparatus according to claim 7, wherein the first latch unit comprises: a switching section configured to output the input signal during the high period of the falling clock; and a signal retaining section configured to latch an output of the switching section, and output the rising synchronization signal. ### Claim 9 (depends on 7) The semiconductor apparatus according to claim 7, wherein the second latch unit comprises: a switching section configured to output the input signal during the high period of the rising clock; and a signal retaining section configured to latch an output of the switching section, and output the falling synchronization signal. ### Claim 10 A semiconductor apparatus comprising: a plurality of semiconductor dies stacked over a base die; a controller electrically coupled to the base die; and a direct access ball electrically coupled to the base die through a substrate, wherein the base die includes a first input/output circuit block which transmits and receives signals to and from the controller, and a second input/output circuit block which transmits and receives signals to and from the direct access ball, wherein the second input/output circuit block converts signals, which are received from the direct access ball and each bit of which has the same data valid window as each other, into at least two kinds of signals, some bits of which have longer data valid windows than the other bits, and outputs the converted signals, and wherein the first input/output circuit block receives output signals of the second input/output circuit block, and outputs signals, each bit of which has the same data valid window as each other, by capturing bits having longer data valid windows than the other bits. ### Claim 11 (depends on 10) The semiconductor apparatus according to claim 10, wherein the second input/output circuit block converts signals, which are received from the direct access ball and each bit of which has the same data valid window as each other, into synchronization signals, some bits of which have longer data valid windows than the other bits, in response to a clock, and outputs the converted signals. ### Claim 12 (depends on 11) The semiconductor apparatus according to claim 11, wherein the synchronization signals include a rising synchronization signal and a falling synchronization signal, and wherein the second input/output circuit block comprises: a first latch unit configured to receive a signal inputted from the direct access ball and output the rising synchronization signal having a certain logic level during a high period of the clock, and retain a level of the rising synchronization signal during a low period of the clock; and a second latch unit configured to receive the signal inputted from the direct access ball and output the falling synchronization signal having a certain logic level during the low period of the clock, and retain a level of the falling synchronization signal during the high period of the clock. ### Claim 13 (depends on 12) The semiconductor apparatus according to claim 12, wherein the first input/output circuit block outputs the rising synchronization signal as an output signal during the high period of the clock, and outputs the falling synchronization signal as the output signal during the low period of the clock. ### Claim 14 A system comprising: a transmission block configured to convert an input signal into two or more synchronization signals, some bits of which have longer data valid windows than the other bits, and output the two or more synchronization signals; and a reception block configured to generate the output signal by capturing bits having longer data valid windows between the two or more synchronization signals, wherein the transmission block alternately outputs the some bits and the other bits in series, wherein the transmission block is configured to convert the input signal into a rising synchronization signal and a falling synchronization signal, and output the rising synchronization signal, a first bit of which has a longer data valid window than a second bit, and the falling synchronization signal, a second bit of which has a longer data valid window than a first bit. ### Claim 15 (depends on 14) The system according to claim 14, wherein the reception block is configured to output a rising synchronization signal, a first bit of which has a longer data valid window than a second bit, as an output signal by capturing the first bit, and output a falling synchronization signal, a second bit of which has a longer data valid window than a first bit, as the output signal by capturing the second bit. ### Claim 16 (depends on 14) The system according to claim 14, wherein the transmission block comprises: a splitter configured to receive the clock, and generate a rising clock and a falling clock; a first latch unit configured to generate a rising synchronization signal by receiving and storing the input signal during a high period of the falling clock and retaining a latched signal during a low period of the falling clock; and a second latch unit configured to generate a falling synchronization signal by receiving and storing the input signal during a high period of the rising clock and retaining a latched signal during a low period of the rising clock. ### Claim 17 (depends on 16) The system according to claim 16, wherein the first latch unit comprises: a switching section configured to output the input signal during the high period of the falling clock; and a signal retaining section configured to latch an output of the switching section, and output the rising synchronization signal. ### Claim 18 (depends on 16) The system according to claim 16, wherein the second latch unit comprises: a switching section configured to output the input signal during the high period of the rising clock; and a signal retaining section configured to latch an output of the switching section, and output the falling synchronization signal.