# US 9,438,377 B2 · LLR computation device and error correction decoding device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,377 B2 - Document ID: US9438377B2 - Status: Granted - Kind: B2 - Application number: 14/343,305 - Filed: 2012-10-05 - Published: 2014-08-14 - Granted: 2016-09-06 - Earliest claimed: 2011-11-28 - Assignees: Mitsubishi Electric Corporation - Applicants: Kenya Sugihara; Wataru Matsumoto - Inventors: Kenya Sugihara; Wataru Matsumoto - Web page: https://patentgrep.com/patent/US9438377B2 ## CPC - H04L 1/0045: {Arrangements at the receiver end} - H03M 13/612: {Aspects specific to channel or signal-to-noise ratio estimation (H03M13/63 takes precedence)} - H03M 13/6337: {Error control coding in combination with channel estimation} - H04L 1/005: {Iterative decoding, including iteration between signal detection and decoding operation} - H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)} - H04L 25/067: {providing soft decisions, i.e. decisions together with an estimate of reliability (H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178)} - H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes} - H04L 27/38: Demodulator circuits; Receiver circuits - H04L 2025/0342: {QAM} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A two-reference-point-pair determining unit 101 determines two reference point pairs by selecting two transmission symbol points with their LLR computation target bit being 0 and two transmission symbol points with their LLR computation target bit being 1. An LLR computation unit 113 assigns weights to the two LLRs calculated for the two reference point pairs, respectively, followed by adding them, and further adds to the addition result a correction term that may be zero sometimes, thus computing LLR for the two reference point pairs. ## Claims ### Claim 1 A Log-Likelihood Ratio (LLR) computation device of a receiver for receiving a signal that is generated by modulating an error-correcting-coded bit string by a multivalued modulation scheme and is transmitted to the receiver, the LLR computation device comprising: a reference-point-pair determination circuitry that determines first/second reference point pairs by selecting two transmission symbol points each of whose k-th bit is 0 and two transmission symbol points each of whose k-th bit is 1, each of the first/second reference point pairs being consisted of a combination of the selected transmission symbol point whose k-th bit is 0 and the selected transmission symbol point whose k-th bit is 1; and an LLR computation unit circuitry that calculates an LLR for a received signal point by calculating a first LLR based on the first reference point pair and the received signal point and also calculating a second LLR based on the second reference point pair and the received signal point, assigning weights to the first/second LLRs and adding up the weighted first/second LLRs, and adding, to a result of the addition of the weighted first/second LLRs, a correction term. ### Claim 2 (depends on 1) The LLR computation device according to claim 1, wherein the LLR computation circuitry assigns equal weights to the first/second LLRs. ### Claim 3 (depends on 1) The LLR computation device according to claim 1, wherein the reference-point-pair determination circuitry determines all or part of the reference point pairs from a transmission symbol point closest in distance to the received signal point. ### Claim 4 (depends on 1) The LLR computation device according to claim 1, wherein the reference-point-pair determination circuitry determines as all or part of the reference points a transmission symbol which is known in advance to be transmitted frequently or always. ### Claim 5 (depends on 1) An error correction decoding device comprising: the LLR computation device as defined in claim 1; and a soft-decision error correction decoder that performs error correction decoding using the LLR computed by the LLR computation device, wherein the LLR computation device determines at least part of the reference point pairs from an error correction decoding intermediate result of the soft-decision error correction decoder; and the soft-decision error correction decoder outputs a final decoding result after repeating the error correction decoding a prescribed number of times. ### Claim 6 (depends on 1) The LLR computation device according to claim 1, wherein the correction term has a value of zero. ### Claim 7 A Log-Likelihood Ratio (LLR) computation device of a receiver for receiving a signal that is generated by modulating an error-correcting-coded bit string by a multivalued modulation scheme and is transmitted to the receiver, the LLR computation device comprising: a reference-point-pair determination circuitry that determines first/second reference point pairs by selecting two transmission symbol points each of whose k-th bit is 0 and two transmission symbol points each of whose k-th bit is 1, each of the first/second reference point pairs being consisted of a combination of the selected transmission symbol point whose k-th bit is 0 and the selected transmission symbol point whose k-th bit is 1; a square difference calculation circuitry that calculates a difference between squared distances from a received signal point to each of the two transmission symbol points whose k-th bit is 0 and also calculate a difference between squared distances from the received signal point to each of the two transmission symbol points whose k-th bit is 1; and an LLR computation circuitry that calculates an LLR for the received signal point by a prescribed LLR computation expression using the differences calculated by the square difference calculation circuitry. ### Claim 8 (depends on 7) The LLR computation device according to claim 7, wherein the LLR computation circuitry performs LLR computation of a kth bit using the following expression, L k = ⁢ ln ⁢ ⁢ ∑ s i ∈ C k , 0 ⁢ exp ⁡ ( -  r - s i  2 2 ⁢ σ 2 ) - ln ⁢ ∑ s i ∈ C k , 1 ⁢ exp ⁡ ( -  r - s i  2 2 ⁢ σ 2 ) ≈ ⁢ ln ⁡ ( exp ⁡ ( -  r - s j  2 2 ⁢ σ 2 ) + exp ⁡ ( -  r - s l  2 2 ⁢ σ 2 ) ) - ⁢ ln ⁡ ( exp ⁡ ( -  r - s j ′  2 2 ⁢ σ 2 ) + exp ⁡ ( -  r - s l ′  2 2 ⁢ σ 2 ) ) ≈ ⁢ - min ⁡ (  r - s j  2 ,  r - s l  2 ) + min ⁡ (  r - s j ′  2 ,  r - s l ′  2 ) 2 ⁢ σ 2 + ⁢ max ⁡ ( 0 , A - 1 4 ⁢ σ 2 ⁢   r - s l  2 -  r - s j  2  ) - ⁢ max ⁡ ( 0 , A - 1 4 ⁢ σ 2 ⁢   r - s l ′  2 -  r - s j ′  2  ) where r is the received signal point, sj and s1 are reference points each of whose kth bit of the two transmission symbols being 0, s′j and s′1 are reference points each of whose kth bit of the two transmission symbols being 1, σ is a standard deviation of Gaussian noise of a communication channel, and A is a constant term. ### Claim 9 (depends on 7) The LLR computation device according to claim 7, wherein the reference-point-pair determination circuitry determines all or part of the reference point pairs from a transmission symbol point closest in distance to the received signal point. ### Claim 10 (depends on 7) The LLR computation device according to claim 7, wherein the reference-point-pair determination circuitry determines as all or part of the reference points a transmission symbol which is known in advance to be transmitted frequently or always. ### Claim 11 (depends on 7) An error correction decoding device comprising: the LLR computation device as defined in claim 7; and a soft-decision error correction decoder that performs error correction decoding using the LLR computed by the LLR computation device, wherein the LLR computation device determines at least part of the reference point pairs from an error correction decoding intermediate result of the soft-decision error correction decoder; and the soft-decision error correction decoder outputs a final decoding result after repeating the error correction decoding a prescribed number of times. ### Claim 12 A Log-Likelihood Ratio (LLR) computation device of a receiver for receiving a signal that is generated by modulating an error-correcting-coded bit string by a multivalued modulation scheme and is transmitted to the receiver, the LLR computation device comprising: a reference-point-pair determination circuitry that determines first/second/third reference point pairs by selecting three transmission symbol points each of whose k-th bit is 0 and three transmission symbol points each of whose k-th bit is 1, each of the first/second/third reference point pairs being consisted of a combination of the selected transmission symbol point whose k-th bit is 0 and the selected transmission symbol point whose k-th bit is 1; and an LLR computation circuitry that calculates an LLR for a received signal point by calculating a first LLR based on the first reference point pair and the received signal point, calculating a second LLR based on the second reference point pair and the received signal point, and also calculating a third LLR based on the third reference point pair and the received signal point, assigning weights to the first/second/third LLRs and adding up the weighted first/second/third LLRs, and adding, to a result of the addition of the weighted first/second/third LLRs, a correction term. ### Claim 13 (depends on 12) The LLR computation device according to claim 12, wherein, when assigning the weights to the first/second/third LLRs, the LLR computation circuitry multiplies, by ½, one of the first/second/third LLRs which is calculated based on one of the first/second/third reference point pairs closest to the received signal point, and multiplies the other two LLRs by ¼. ### Claim 14 (depends on 12) The LLR computation device according to claim 12, wherein the reference-point-pair determination circuitry determines all or part of the reference point pairs from a transmission symbol point closest in distance to the received signal point. ### Claim 15 (depends on 12) The LLR computation device according to claim 12, wherein the reference-point-pair determination circuitry determines as all or part of the reference points a transmission symbol which is known in advance to be transmitted frequently or always. ### Claim 16 (depends on 12) An error correction decoding device comprising: the LLR computation device as defined in claim 12; and a soft-decision error correction decoder that performs error correction decoding using the LLR computed by the LLR computation device, wherein the LLR computation device determines at least part of the reference point pairs from an error correction decoding intermediate result of the soft-decision error correction decoder; and the soft-decision error correction decoder outputs a final decoding result after repeating the error correction decoding a prescribed number of times. ### Claim 17 A Log-Likelihood Ratio (LLR) computation device of a receiver for receiving a signal that is generated by modulating an error-correcting-coded bit string by a multivalued modulation scheme and is transmitted to the receiver, the LLR computation device comprising: a reference-point-pair determination circuitry that determines four or more reference point pairs by selecting four or more transmission symbol points each of whose k-th bit is 0 and four or more transmission symbol points each of whose k-th bit is 1, each of the reference point pairs being consisted of a combination of the selected transmission symbol point whose k-th bit is 0 and the selected transmission symbol point whose k-th bit is 1; and an LLR computation circuitry that calculates an LLR for a received signal point by calculating four or more LLRs based on the individual reference point pairs and the received signal point, assigning weights to the four or more LLRs and adding up the weighted LLRs, and adding, to a result of the addition of the weighted LLRs, a correction term. ### Claim 18 (depends on 17) The LLR computation device according to claim 17, wherein the reference-point-pair determination circuitry determines all or part of the reference point pairs from a transmission symbol point closest in distance to the received signal point. ### Claim 19 (depends on 17) The LLR computation device according to claim 17, wherein the reference-point-pair determination circuitry determines as all or part of the reference points a transmission symbol which is known in advance to be transmitted frequently or always. ### Claim 20 (depends on 17) An error correction decoding device comprising: the LLR computation device as defined in claim 17; and a soft-decision error correction decoder that performs error correction decoding using the LLR computed by the LLR computation device, wherein the LLR computation device determines at least part of the reference point pairs from an error correction decoding intermediate result of the soft-decision error correction decoder; and the soft-decision error correction decoder outputs a final decoding result after repeating the error correction decoding a prescribed number of times.