# US 9,438,301 B2 · PLL circuit, calibration method, and wireless communication apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,438,301 B2 - Document ID: US9438301B2 - Status: Granted - Kind: B2 - Application number: 14/409,239 - Filed: 2014-03-31 - Published: 2016-02-04 - Granted: 2016-09-06 - Earliest claimed: 2013-04-19 - Assignees: Panasonic Intellectual Property Management Co., Ltd. - Applicants: Panasonic Intellectual Property Management Co., Ltd. - Inventors: Yoichi Nagaso; Kenji Miyanaga; Takahiro Shima - Web page: https://patentgrep.com/patent/US9438301B2 ## CPC - H04B 1/403: using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency - H03L 7/099: concerning mainly the controlled oscillator of the loop - H03L 7/183: a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number {(H03L7/1806 takes precedence)} - H04L 27/20: Modulator circuits; Transmitter circuits - H04L 27/22: Demodulator circuits; Receiver circuits - H03L 7/0995: {the oscillator comprising a ring oscillator} - H03L 2207/06: Phase locked loops with a controlled oscillator having at least two frequency control terminals - H04B: TRANSMISSION - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract In the stop state of a VCO and an injection locked frequency divider, an ILFD controller sets the control parameter of an injection locked frequency divider on the basis of the frequencies of a reference signal and the frequency-divided signal measured according to the control parameter of the injection locked frequency divider. While the injection locked frequency divider is operated and in the stop state of the VCO, the ILFD controller sets the control parameter of the injection locked frequency divider on the basis of the frequencies of the reference signal and the frequency-divided signal measured according to the control parameter of the injection locked frequency divider. ## Claims ### Claim 1 A PLL circuit comprising: a voltage controlled oscillator that outputs a high-frequency signal; a first injection locked frequency divider that generates a first frequency-divided signal obtained by frequency-dividing the output high-frequency signal; a second injection locked frequency divider that generates a second frequency-divided signal obtained by frequency-dividing the first frequency-divided signal; a frequency divider that generates a third frequency-divided signal obtained by frequency-dividing the second frequency-divided signal so as to be a frequency of a reference signal; a phase and frequency comparator that compares the third frequency-divided signal with the reference signal and that outputs the difference between phase and frequency; a charge pump that converts the output difference into current or voltage; a loop filter that generates the control voltage of the voltage controlled oscillator according to the converted current or voltage and that applies the generated control voltage to the voltage controlled oscillator; and a calibration circuit that selects an oscillation band for determining the oscillation frequency of the voltage controlled oscillator, and that adjusts a first control parameter of the first injection locked frequency divider and a second control parameter of the second injection locked frequency divider, for operating the first injection locked frequency divider and the second injection locked frequency divider at different operation bands, wherein after adjusting the second control parameter, the calibration circuit adjusts the first control parameter, and adjusts the oscillation band of the voltage controlled oscillator according to the third frequency-divided signal. ### Claim 2 (depends on 1) The PLL circuit according to claim 1, wherein the calibration circuit further includes a first bias generation circuit that generates the first control parameter to be used for the frequency division of the high-frequency signal in correspondence with fluctuation in temperature. ### Claim 3 (depends on 1) The PLL circuit according to claim 1, wherein the calibration circuit further includes: a clock counter that measures the frequencies of the third frequency-divided signal and the reference signal; and a first bias generation circuit that generates the first control parameter to be used for the frequency division of the high-frequency signal in correspondence with fluctuation in temperature and to be used for adjusting the measured frequency of the second frequency-divided signal. ### Claim 4 (depends on 3) The PLL circuit according to claim 3, wherein as a setting value of the first control parameter, the calibration circuit uses a result of the addition of an initial value of the first control parameter, a value related to the second control parameter, and a constant, wherein the first control parameter is generated in correspondence with fluctuation in temperature; and wherein the value related to the second control parameter is a value obtained by the multiplication of the difference between the second control parameter after the adjustment and the second control parameter before the adjustment by a constant coefficient. ### Claim 5 (depends on 1) The PLL circuit according to claim 1, wherein the calibration circuit further includes: a second bias generation circuit that generates a control parameter to be used as the second control parameter for the frequency division of the first frequency-divided signal; a third bias generation circuit that generates a control parameter to be used as the second control parameter for the frequency division of the first frequency-divided signal in correspondence with fluctuation in temperature in correspondence with fluctuation in temperature with time; and a bias selection circuit that selects the second control parameter generated by the second bias generation circuit or the second control parameter generated by the third bias generation circuit. ### Claim 6 (depends on 5) The PLL circuit according to claim 5, wherein as a setting value of the first control parameter, the calibration circuit uses a result of the addition of an initial value of the first control parameter, a value related to the second control parameter, and a constant, wherein the first control parameter is generated in correspondence with fluctuation in temperature; and wherein the value related to the second control parameter is a value obtained by the multiplication of the difference between the second control parameter after the adjustment and the second control parameter before the adjustment by a constant coefficient. ### Claim 7 (depends on 1) The PLL circuit according to claim 1, wherein the calibration circuit further includes: a clock counter that measures the frequencies of the third frequency-divided signal frequency-divided according to the control parameter of the second injection locked frequency divider and the reference signal; a second bias generation circuit that generates a control parameter to be used as the second control parameter for the frequency division of the first frequency-divided signal and to be used for adjusting the measured frequency of the second frequency-divided signal; a third bias generation circuit that generates a control parameter to be used as the second control parameter for the frequency division of the first frequency-divided signal in correspondence with fluctuation in temperature and to be used for adjusting the measured frequency of the second frequency-divided signal; and a bias selection circuit that selects the second control parameter generated by the second bias generation circuit or the second control parameter generated by the third bias generation circuit. ### Claim 8 (depends on 1) The PLL circuit according to claim 1, wherein the calibration circuit further includes: a VCO controller that controls an operation of the voltage controlled oscillator; and an ILFD controller that controls operations of the first injection locked frequency divider and the second injection locked frequency divider; and wherein the ILFD controller stops the voltage controlled oscillator in the case that the ILFD controller adjusts the first control parameter and the second control parameter. ### Claim 9 (depends on 8) The PLL circuit according to claim 8, wherein the VCO controller releases the stop of the voltage controlled oscillator after the adjustment of the first control parameter and selects the oscillation band for determining the oscillation frequency of the voltage controlled oscillator. ### Claim 10 (depends on 8) The PLL circuit according to claim 8, wherein according to the frequency differences between the reference signal and the frequency-divided signals obtained by frequency-dividing the high-frequency signal from the voltage controlled oscillator according to the selected oscillation band by the first injection locked frequency divider, by the second injection locked frequency divider and by the frequency divider, the VCO controller selects another oscillation band of the voltage controlled oscillator. ### Claim 11 (depends on 1) A wireless communication apparatus comprising: the PLL circuit according to claim 1; a modulator that modulates a baseband transmission signal; a transmission mixer that generates a high-frequency signal using the first local signal generated by the PLL circuit and the modulated transmission signal; a receiving mixer that generates a baseband reception signal using the second local signal generated by the PLL circuit and a received high-frequency reception signal; and a demodulator that demodulates the generated baseband reception signal. ### Claim 12 A calibration method in a PLL circuit in which a first injection locked frequency divider is connected to a second injection locked frequency divider, the calibration method comprising the steps of: stopping operations of a voltage controlled oscillator for outputting a high-frequency signal and the first injection locked frequency divider; measuring frequencies of a predetermined reference signal and the frequency-divided signal output from a frequency divider for frequency-dividing an output signal of the second injection locked frequency divider according to a second control parameter of the second injection locked frequency divider; adjusting the second control parameter on the basis of the measured frequency of the frequency-divided signal; releasing the stop of the first injection locked frequency divider; frequency-dividing the output signal of the first injection locked frequency divider by the second injection locked frequency divider according to the first control parameter of the first injection locked frequency divider; measuring the frequencies of the predetermined reference signal and a frequency-divided signal output from the frequency divider again, the frequency divider frequency-dividing the output signal of the second injection locked frequency divider; adjusting the first control parameter on the basis of the frequency of the frequency divided signal output after the re-measurement; releasing the stop of the voltage controlled oscillator; selecting an oscillation band for determining the oscillation frequency of the voltage controlled oscillator; and selecting the oscillation band of the voltage controlled oscillator on the basis of the frequencies of the frequency-divided signals obtained by frequency-dividing the output signal of the voltage controlled oscillator according to the selected oscillation band by the first injection locked frequency divider, by the second injection locked frequency divider and by the frequency divider.