# US 9,438,272 B1 · Digital phase locked loop circuitry and methods

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,438,272 B1
- Document ID: US9438272B1
- Status: Granted
- Kind: B1
- Application number: 14/331,933
- Filed: 2014-07-15
- Granted: 2016-09-06
- Earliest claimed: 2003-01-21
- Assignees: Altera Corporation
- Applicants: Altera Corporation
- Inventors: Ramanand Venkata; Chong H. Lee
- Web page: https://patentgrep.com/patent/US9438272B1

## CPC

- H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00)
- H03L 7/089: the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence)
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- H04L 7/0337: {Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals}
- H03L 2207/50: All digital phase-locked loop
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

## Claims

### Claim 1

Apparatus for converting parallel data to serial data, the apparatus comprising:
serializer circuitry for:
receiving, at a first clock rate, the parallel data; and
outputting, at a second clock rate, each bit of the parallel data, one bit after another in succession; and
circuitry for replicating each bit that is output by the serializer onto a number of parallel leads, wherein the number is based on a ratio of the first clock rate and the second clock rate.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the serializer circuitry is first serializer circuitry, the apparatus further comprising second serializer circuitry for:
receiving, in parallel, signals from the number of parallel leads; and
outputting each of the signals, one signal after another, on a serial output lead.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the second clock rate is larger than the first clock rate.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the circuitry is clocked by a clock having the second clock rate.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein width of the parallel data is selectable.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the number of parallel leads is selectable.

### Claim 7 (depends on 1)

The apparatus of claim 1, further comprising routing circuitry operable to selectively substitute the parallel data for outputs of the serializer circuitry on the number of parallel leads.

### Claim 8 (depends on 1)

The apparatus of claim 1, further comprising divider circuitry operable to divide a clock signal having the second clock rate to obtain the first clock rate.

### Claim 9

A method for converting parallel data to serial data, the method comprising:
receiving, at a first clock rate, the parallel data;
generating, at a second clock rate, a first set of serial data comprising each bit of the parallel data arranged one bit after another in succession; and
replicating each bit of the first set of serial data onto a number of parallel leads, wherein the number is based on a ratio of the first clock rate and the second clock rate.

### Claim 10 (depends on 9)

The method of claim 9, wherein the second clock rate is larger than the first clock rate.

### Claim 11 (depends on 9)

The method of claim 9, wherein width of the parallel data is selectable.

### Claim 12 (depends on 9)

The method of claim 9, wherein the parallel data is first parallel data, the method further comprising:
selectively substituting, in second parallel data, the first parallel data for the number of instances, arranged in parallel, of each successive bit of the first set of serial data, wherein the second parallel data comprises the number of instances, arranged in parallel, of each successive bit of the first set of serial data.

### Claim 13 (depends on 9)

The method of claim 9, further comprising dividing a clock signal having the second clock rate to obtain the first clock rate.

### Claim 14

Apparatus for converting parallel data to serial data, the apparatus comprising:
serializer circuitry for:
receiving, at a first clock rate, a first set of parallel data; and
generating, at a second clock rate, a first set of serial data comprising each bit of the first set of parallel data arranged one bit after another in succession; and
circuitry for generating a second set of parallel data comprising a number of instances, arranged in parallel, of each successive bit of the first set of serial data, wherein the number is based on a ratio of the first clock rate and the second clock rate.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the serializer circuitry is first serializer circuitry, the apparatus further comprising second serializer circuitry for generating a second set of serial data, the second set of serial data comprising each bit of the second set of parallel data arranged one bit after another in succession.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the second clock rate is larger than the first clock rate.

### Claim 17 (depends on 14)

The apparatus of claim 14, wherein the circuitry is clocked by a clock having the second clock rate.

### Claim 18 (depends on 14)

The apparatus of claim 14, wherein width of the first set of parallel data is selectable.

### Claim 19 (depends on 14)

The apparatus of claim 14, wherein width of the second set of parallel data is selectable.

### Claim 20 (depends on 14)

The apparatus of claim 14, further comprising divider circuitry operable to divide a clock signal having the second clock rate to obtain the first clock rate.