# US 9,438,265 B2 · Phase multiplexer

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- Number: US 9,438,265 B2
- Document ID: US9438265B2
- Status: Granted
- Kind: B2
- Application number: 14/155,327
- Filed: 2014-01-14
- Published: 2015-10-22
- Granted: 2016-09-06
- Earliest claimed: 2014-01-14
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Paolo Madoglio; Stefano Pellerano
- Web page: https://patentgrep.com/patent/US9438265B2

## CPC

- H03M 1/822: {using pulse width modulation}
- G06F 1/08: Clock generators with changeable or programmable clock frequency
- H03K 5/131: Digitally controlled
- H03M 1/0836: {of phase error, e.g. jitter}
- H03M 1/662: {Multiplexed conversion systems}
- G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom
- H03K 2005/00045: {DC voltage control of a capacitor or of the coupling of a capacitor as a load}
- H03L 7/16: Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

Representative implementations of devices and techniques provide a phase multiplexer that may be associated with at least a communication device. The described phase multiplexer may be able to switch between input phases without distorting a pulse width of a given input phase. In one implementation, this is achieved by enabling one phase at a time. More specifically, a gating window specific for each given phase is provided. The gating window is designed to avoid glitches associated with signals at an output of the phase multiplexer. Furthermore, the gating window is designed to avoid the generation of pulse width modifications.

## Claims

### Claim 1

A digital to time converter, comprising:
a processing element to provide a plurality of phase signals;
a multiplexer circuit coupled to the processing element and including an input flip-flop element, the multiplexer circuit configured to receive the plurality of phase signals, to receive digital time information at the input flip-flop element, and to process a first signal of the plurality of phase signals during a first gating window and a second signal of the plurality of phase signals during a second gating window using one or more digital words provided by the input flip-flop element;
wherein the first and second gating windows are unique from one another; and
wherein an output of the multiplexer is configured to trigger the input flip-flop element.

### Claim 2 (depends on 1)

The digital to time converter according to claim 1, wherein the processing element comprises a plurality of the delay elements, each of the plurality of delay elements providing a phase of the plurality of phases.

### Claim 3 (depends on 1)

The digital to time converter according to claim 1, wherein the processing element comprises a divider element to provide the plurality of phases spaced across a single period of a frequency signal.

### Claim 4 (depends on 1)

The digital to time converter according to claim 1, wherein the multiplexer circuit comprises a first flip-flop coupled to a first logic element, the first flip-flop and the first logic element configured to provide the first gating window to process the first signal of the plurality of phase signals.

### Claim 5 (depends on 4)

The digital time converter according to claim 4, wherein the multiplexer circuit further comprises a second flip-flop coupled to a second logic element, the second flip-flop and a second logic element configured to provide the second gating window to process the second signal of the plurality of phase signals.

### Claim 6 (depends on 5)

The digital time converter according to claim 5, wherein the first logic element is a first AND gate and the second logic element is a second AND gate.

### Claim 7 (depends on 4)

The digital time converter according to claim 4, wherein the first flip-flop includes a first and second input, the first input to receive a digital word of the one or more digital words and the second input to receive the first signal of the plurality of phase signals, the first flip-flop further including an output to provide an enable signal to a first input associated with the first logic element, the first logic element further to receive the first signal of the plurality of phase signals on a second input associated with the first logic element.

### Claim 8 (depends on 4)

The digital time converter according to claim 4, wherein the first flip-flop includes a first and second input, the first input to receive a digital word of the one or more digital words and the second input to receive the first signal of the plurality of phase signals, the first flip-flop further including an output to provide an enable signal to a first input associated with the first logic element, the first logic element further to receive the second signal of the plurality of phase signals on a second input associated with the first logic element.

### Claim 9 (depends on 5)

The digital tune converter according to claim 5, wherein the second flip-flop includes a first and second input, the first input to receive a digital word of the one or more digital words and the second input to receive the second signal of the plurality of phase signals, the second flip-flop further including an output to provide an enable signal to a first input associated with the second logic element, the second logic element further to receive the second signal of the plurality of phase signals on a second input associated with the second logic element.

### Claim 10 (depends on 5)

The digital time converter according to claim 5, wherein the second flip-flop includes a first and second input, the first input to receive a digital word of the one or more digital words and the second input to receive the second signal of the plurality of phase signals, the second flip-flop further including an output to provide an enable signal to a first input associated with the second logic element, the second logic element further to receive the first signal of the plurality of phase signals on a second input associated with the second logic element.

### Claim 11

A device, comprising:
a multiplexer circuit to receive a plurality of phase signals, the multiplexer circuit including:
a first plurality of circuit elements to process a first phase signal of the plurality of phase signals;
a second plurality of circuit elements to process a second phase signal of the plurality of phase signals; and
a flip-flop that is coupled to the first plurality of circuit elements and further coupled to the second plurality of circuit elements the flip-flop to provide a first digital word to the first product circuit elements and provide a second digital word to the second plurality of circuit elements;
wherein the flip-flop is triggered by a frequency signal provided at an output of the multiplexer circuit.

### Claim 12 (depends on 11)

The device according to claim 11, wherein the first plurality of circuit elements processes the first phase signal over a first time period and the second plurality of circuit elements processes the second phase signal over a second time period, the first time period being at least partly different from the second time period.

### Claim 13 (depends on 11)

The device according to claim 11, wherein the first plurality of circuit elements comprises a flip-flop coupled to an input of an AND gate.

### Claim 14 (depends on 11)

The device according to claim 11, wherein the second plurality of circuit elements comprises a flip-flop coupled to an input of an AND gate.

### Claim 15 (depends on 11)

The device according to claim 11, wherein the multiplexer circuit further includes a logic element coupled to a first output of the first plurality of circuit elements and further coupled to a second output of the second plurality of circuit elements, the logic element to receive the first phase signal from the first plurality of circuit elements and to receive the second phase signal from the second plurality of circuit elements.

### Claim 16 (depends on 15)

The device according to claim 15, wherein the logic element is an OR gate.

### Claim 17 (depends on 11)

The device according to claim 11, wherein the device is a digital to time converter.